mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
Correct some load / store instruction itinerary mistakes:
1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
5ed5c38423
commit
d2ca813549
@ -169,7 +169,7 @@ class VLD1D<bits<4> op7_4, string Dt>
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"vld1", Dt, "\\{$dst\\}, $addr", "", []>;
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class VLD1Q<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2),
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(ins addrmode6:$addr), IIC_VLD2,
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(ins addrmode6:$addr), IIC_VLD1x2,
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"vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>;
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def VLD1d8 : VLD1D<0b0000, "8">;
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@ -182,20 +182,20 @@ def VLD1q16 : VLD1Q<0b0100, "16">;
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def VLD1q32 : VLD1Q<0b1000, "32">;
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def VLD1q64 : VLD1Q<0b1100, "64">;
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def VLD1q8Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD1q16Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD1q32Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD1q64Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
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def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
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def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
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def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
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// ...with address register writeback:
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class VLD1DWB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1,
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1u,
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"vld1", Dt, "\\{$dst\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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class VLD1QWB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1x2u,
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"vld1", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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@ -209,19 +209,19 @@ def VLD1q16_UPD : VLD1QWB<0b0100, "16">;
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def VLD1q32_UPD : VLD1QWB<0b1000, "32">;
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def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
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def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
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def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
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def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
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def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
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// ...with 3 registers (some of these are only for the disassembler):
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class VLD1D3<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr), IIC_VLD3, "vld1", Dt,
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(ins addrmode6:$addr), IIC_VLD1x3, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
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class VLD1D3WB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD3, "vld1", Dt,
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1x3u, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
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def VLD1d8T : VLD1D3<0b0000, "8">;
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@ -234,13 +234,13 @@ def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
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def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
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def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">;
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def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD3>;
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def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
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def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
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def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
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// ...with 4 registers (some of these are only for the disassembler):
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class VLD1D4<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr), IIC_VLD4, "vld1", Dt,
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(ins addrmode6:$addr), IIC_VLD1x4, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
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class VLD1D4WB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0010,op7_4,
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@ -259,8 +259,8 @@ def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
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def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
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def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
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def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD4>;
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def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
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def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
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// VLD2 : Vector Load (multiple 2-element structures)
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class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -270,7 +270,7 @@ class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
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class VLD2Q<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, 0b0011, op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr), IIC_VLD4,
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(ins addrmode6:$addr), IIC_VLD2x2,
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"vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
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def VLD2d8 : VLD2D<0b1000, 0b0000, "8">;
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@ -285,20 +285,20 @@ def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
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def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD4>;
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def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD4>;
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def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD4>;
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def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
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def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
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def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
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// ...with address register writeback:
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class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD2u,
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"vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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class VLD2QWB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, 0b0011, op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD4,
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD2x2u,
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"vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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@ -310,13 +310,13 @@ def VLD2q8_UPD : VLD2QWB<0b0000, "8">;
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def VLD2q16_UPD : VLD2QWB<0b0100, "16">;
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def VLD2q32_UPD : VLD2QWB<0b1000, "32">;
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def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>;
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def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
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def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
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def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
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def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>;
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def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
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def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
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def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
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// ...with double-spaced registers (for disassembly only):
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def VLD2b8 : VLD2D<0b1001, 0b0000, "8">;
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@ -455,29 +455,29 @@ class VLDQQQQLNWBPseudo<InstrItinClass itin>
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class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
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IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
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IIC_VLD2ln, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr",
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"$src1 = $dst1, $src2 = $dst2", []>;
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def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">;
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def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">;
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def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">;
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def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2>;
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def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2>;
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def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2>;
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def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
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def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
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def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
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// ...with double-spaced registers:
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def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">;
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def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">;
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def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2>;
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def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2>;
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def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
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def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
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// ...with address register writeback:
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class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset,
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DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt,
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DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
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"\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset",
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"$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>;
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@ -485,15 +485,15 @@ def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">;
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def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">;
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def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">;
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def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2>;
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def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2>;
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def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2>;
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def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
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def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
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def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
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def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">;
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def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">;
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def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2>;
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def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2>;
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def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
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def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
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// VLD3LN : Vector Load (single 3-element structure to one lane)
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class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
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@ -127,7 +127,19 @@ def IIC_fpStore64 : InstrItinClass;
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def IIC_fpStore_m : InstrItinClass<0>; // micro-coded
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def IIC_fpStore_mu : InstrItinClass<0>; // micro-coded
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def IIC_VLD1 : InstrItinClass;
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def IIC_VLD1x2 : InstrItinClass;
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def IIC_VLD1x3 : InstrItinClass;
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def IIC_VLD1x4 : InstrItinClass;
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def IIC_VLD1u : InstrItinClass;
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def IIC_VLD1x2u : InstrItinClass;
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def IIC_VLD1x3u : InstrItinClass;
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def IIC_VLD1x4u : InstrItinClass;
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def IIC_VLD2 : InstrItinClass;
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def IIC_VLD2x2 : InstrItinClass;
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def IIC_VLD2u : InstrItinClass;
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def IIC_VLD2x2u : InstrItinClass;
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def IIC_VLD2ln : InstrItinClass;
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def IIC_VLD2lnu : InstrItinClass;
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def IIC_VLD3 : InstrItinClass;
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def IIC_VLD4 : InstrItinClass;
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def IIC_VST : InstrItinClass;
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@ -14,18 +14,16 @@
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//
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// Scheduling information derived from "Cortex-A8 Technical Reference Manual".
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// Functional Units.
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def A8_Issue : FuncUnit; // issue
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def A8_Pipe0 : FuncUnit; // pipeline 0
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def A8_Pipe1 : FuncUnit; // pipeline 1
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def A8_LdSt0 : FuncUnit; // pipeline 0 load/store
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def A8_LdSt1 : FuncUnit; // pipeline 1 load/store
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def A8_LSPipe : FuncUnit; // Load / store pipeline
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def A8_NPipe : FuncUnit; // NEON ALU/MUL pipe
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def A8_NLSPipe : FuncUnit; // NEON LS pipe
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//
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// Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
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//
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def CortexA8Itineraries : ProcessorItineraries<
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[A8_Issue, A8_Pipe0, A8_Pipe1, A8_LdSt0, A8_LdSt1, A8_NPipe, A8_NLSPipe],
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[A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
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[], [
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// Two fully-pipelined integer ALU pipelines
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//
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@ -104,203 +102,133 @@ def CortexA8Itineraries : ProcessorItineraries<
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// Integer load pipeline
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//
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// loads have an extra cycle of latency, but are fully pipelined
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// use A8_Issue to enforce the 1 load/store per cycle limit
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//
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// Immediate offset
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InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Issue], 0>,
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InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_LdSt0]>], [3, 1]>,
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InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Issue], 0>,
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InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_LdSt0]>], [3, 1]>,
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InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Issue], 0>,
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InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_LdSt0]>], [3, 1]>,
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InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_LSPipe]>], [3, 1]>,
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InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_LSPipe]>], [3, 1]>,
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InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<1, [A8_LSPipe]>], [3, 1]>,
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//
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// Register offset
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InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Issue], 0>,
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InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
|
||||
//
|
||||
// Scaled register offset, issues over 2 cycles
|
||||
InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0], 0>,
|
||||
InstrStage<1, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [4, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0], 0>,
|
||||
InstrStage<1, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [4, 1, 1]>,
|
||||
// FIXME: lsl by 2 takes 1 cycle.
|
||||
InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>,
|
||||
//
|
||||
// Immediate offset with update
|
||||
InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 2, 1]>,
|
||||
InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 2, 1]>,
|
||||
InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
|
||||
InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>,
|
||||
//
|
||||
// Register offset with update
|
||||
InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 2, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>,
|
||||
//
|
||||
// Scaled register offset with update, issues over 2 cycles
|
||||
InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0], 0>,
|
||||
InstrStage<1, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [4, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0], 0>,
|
||||
InstrStage<1, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [4, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [4, 3, 1, 1]>,
|
||||
//
|
||||
// Load multiple, def is the 5th operand.
|
||||
InstrItinData<IIC_iLoad_m , [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<2, [A8_Pipe0], 0>,
|
||||
InstrStage<2, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [1, 1, 1, 1, 3]>,
|
||||
// Load multiple, def is the 5th operand. Pipeline 0 only.
|
||||
// FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
|
||||
InstrItinData<IIC_iLoad_m , [InstrStage<1, [A8_Pipe0]>,
|
||||
InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>,
|
||||
//
|
||||
// Load multiple + update, defs are the 1st and 5th operands.
|
||||
InstrItinData<IIC_iLoad_mu , [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<2, [A8_Pipe0], 0>,
|
||||
InstrStage<2, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [2, 1, 1, 1, 3]>,
|
||||
InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A8_Pipe0]>,
|
||||
InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>,
|
||||
//
|
||||
// Load multiple plus branch
|
||||
InstrItinData<IIC_iLoad_mBr, [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<2, [A8_Pipe0], 0>,
|
||||
InstrStage<2, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>,
|
||||
InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A8_Pipe0]>,
|
||||
InstrStage<3, [A8_LSPipe]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
|
||||
[1, 2, 1, 1, 3]>,
|
||||
//
|
||||
// Pop, def is the 3rd operand.
|
||||
InstrItinData<IIC_iPop , [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<2, [A8_Pipe0], 0>,
|
||||
InstrStage<2, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [1, 1, 3]>,
|
||||
InstrItinData<IIC_iPop , [InstrStage<1, [A8_Pipe0]>,
|
||||
InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>,
|
||||
//
|
||||
// Push, def is the 3th operand.
|
||||
InstrItinData<IIC_iPop_Br, [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<2, [A8_Pipe0], 0>,
|
||||
InstrStage<2, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>,
|
||||
InstrItinData<IIC_iPop_Br, [InstrStage<1, [A8_Pipe0]>,
|
||||
InstrStage<3, [A8_LSPipe]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>],
|
||||
[1, 1, 3]>,
|
||||
|
||||
//
|
||||
// iLoadi + iALUr for t2LDRpci_pic.
|
||||
InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>,
|
||||
InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
|
||||
|
||||
|
||||
// Integer store pipeline
|
||||
//
|
||||
// use A8_Issue to enforce the 1 load/store per cycle limit
|
||||
//
|
||||
// Immediate offset
|
||||
InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1]>,
|
||||
InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1]>,
|
||||
InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 1]>,
|
||||
InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 1]>,
|
||||
//
|
||||
// Register offset
|
||||
InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>,
|
||||
//
|
||||
// Scaled register offset, issues over 2 cycles
|
||||
InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0], 0>,
|
||||
InstrStage<1, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0], 0>,
|
||||
InstrStage<1, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_si , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>,
|
||||
//
|
||||
// Immediate offset with update
|
||||
InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [2, 3, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [2, 3, 1]>,
|
||||
InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>,
|
||||
//
|
||||
// Register offset with update
|
||||
InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [2, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>,
|
||||
//
|
||||
// Scaled register offset with update, issues over 2 cycles
|
||||
InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0], 0>,
|
||||
InstrStage<1, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0], 0>,
|
||||
InstrStage<1, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [3, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_siu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_siu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>,
|
||||
//
|
||||
// Store multiple
|
||||
InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<2, [A8_Pipe0], 0>,
|
||||
InstrStage<2, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>]>,
|
||||
// Store multiple. Pipeline 0 only.
|
||||
// FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
|
||||
InstrItinData<IIC_iStore_m , [InstrStage<1, [A8_Pipe0]>,
|
||||
InstrStage<2, [A8_LSPipe]>]>,
|
||||
//
|
||||
// Store multiple + update
|
||||
InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<2, [A8_Pipe0], 0>,
|
||||
InstrStage<2, [A8_Pipe1]>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0]>], [2]>,
|
||||
InstrItinData<IIC_iStore_mu, [InstrStage<1, [A8_Pipe0]>,
|
||||
InstrStage<2, [A8_LSPipe]>], [2]>,
|
||||
|
||||
// Branch
|
||||
//
|
||||
@ -410,100 +338,127 @@ def CortexA8Itineraries : ProcessorItineraries<
|
||||
InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
|
||||
//
|
||||
// Single-precision FP Load
|
||||
// use A8_Issue to enforce the 1 load/store per cycle limit
|
||||
InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<2, [A8_NLSPipe]>],
|
||||
InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>],
|
||||
[2, 1]>,
|
||||
//
|
||||
// Double-precision FP Load
|
||||
// use A8_Issue to enforce the 1 load/store per cycle limit
|
||||
InstrItinData<IIC_fpLoad64, [InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<2, [A8_NLSPipe]>],
|
||||
InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>],
|
||||
[2, 1]>,
|
||||
//
|
||||
// FP Load Multiple
|
||||
// use A8_Issue to enforce the 1 load/store per cycle limit
|
||||
InstrItinData<IIC_fpLoad_m, [InstrStage<3, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<1, [A8_NLSPipe]>], [1, 1, 1, 2]>,
|
||||
// FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
|
||||
InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>,
|
||||
//
|
||||
// FP Load Multiple + update
|
||||
InstrItinData<IIC_fpLoad_mu,[InstrStage<3, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<1, [A8_NLSPipe]>], [2, 1, 1, 1, 2]>,
|
||||
InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>,
|
||||
//
|
||||
// Single-precision FP Store
|
||||
// use A8_Issue to enforce the 1 load/store per cycle limit
|
||||
InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<2, [A8_NLSPipe]>],
|
||||
InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>],
|
||||
[1, 1]>,
|
||||
//
|
||||
// Double-precision FP Store
|
||||
// use A8_Issue to enforce the 1 load/store per cycle limit
|
||||
InstrItinData<IIC_fpStore64,[InstrStage<2, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<2, [A8_NLSPipe]>],
|
||||
InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>],
|
||||
[1, 1]>,
|
||||
//
|
||||
// FP Store Multiple
|
||||
// use A8_Issue to enforce the 1 load/store per cycle limit
|
||||
InstrItinData<IIC_fpStore_m,[InstrStage<3, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<1, [A8_NLSPipe]>], [1, 1, 1, 1]>,
|
||||
InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>,
|
||||
//
|
||||
// FP Store Multiple + update
|
||||
InstrItinData<IIC_fpStore_mu,[InstrStage<3, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<1, [A8_NLSPipe]>], [2, 1, 1, 1, 1]>,
|
||||
InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>,
|
||||
|
||||
// NEON
|
||||
// Issue through integer pipeline, and execute in NEON unit.
|
||||
//
|
||||
// VLD1
|
||||
// FIXME: We don't model this instruction properly
|
||||
InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<1, [A8_NLSPipe]>]>,
|
||||
InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>]>,
|
||||
// VLD1x2
|
||||
InstrItinData<IIC_VLD1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<2, [A8_NLSPipe], 1>,
|
||||
InstrStage<2, [A8_LSPipe]>],
|
||||
[2, 2, 1]>,
|
||||
//
|
||||
// VLD1x3
|
||||
InstrItinData<IIC_VLD1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<3, [A8_NLSPipe], 1>,
|
||||
InstrStage<3, [A8_LSPipe]>],
|
||||
[2, 2, 3, 1]>,
|
||||
//
|
||||
// VLD1x4
|
||||
InstrItinData<IIC_VLD1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<3, [A8_NLSPipe], 1>,
|
||||
InstrStage<3, [A8_LSPipe]>],
|
||||
[2, 2, 3, 3, 1]>,
|
||||
//
|
||||
// VLD1u
|
||||
InstrItinData<IIC_VLD1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>],
|
||||
[2, 2, 1]>,
|
||||
//
|
||||
// VLD1x2u
|
||||
InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<2, [A8_NLSPipe], 1>,
|
||||
InstrStage<2, [A8_LSPipe]>],
|
||||
[2, 2, 2, 1]>,
|
||||
//
|
||||
// VLD1x3u
|
||||
InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<3, [A8_NLSPipe], 1>,
|
||||
InstrStage<3, [A8_LSPipe]>],
|
||||
[2, 2, 3, 2, 1]>,
|
||||
//
|
||||
// VLD1x4u
|
||||
InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<3, [A8_NLSPipe], 1>,
|
||||
InstrStage<3, [A8_LSPipe]>],
|
||||
[2, 2, 3, 3, 2, 1]>,
|
||||
//
|
||||
// VLD2
|
||||
// FIXME: We don't model this instruction properly
|
||||
InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<1, [A8_NLSPipe]>], [2, 2, 1]>,
|
||||
InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [2, 2, 1]>,
|
||||
//
|
||||
// VLD3
|
||||
// FIXME: We don't model this instruction properly
|
||||
InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 1]>,
|
||||
InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [2, 2, 2, 1]>,
|
||||
//
|
||||
// VLD4
|
||||
// FIXME: We don't model this instruction properly
|
||||
InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<1, [A8_NLSPipe]>], [2, 2, 2, 2, 1]>,
|
||||
InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>], [2, 2, 2, 2, 1]>,
|
||||
//
|
||||
// VST
|
||||
// FIXME: We don't model this instruction properly
|
||||
InstrItinData<IIC_VST, [InstrStage<1, [A8_Issue], 0>,
|
||||
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_LdSt0], 0>,
|
||||
InstrStage<1, [A8_NLSPipe]>]>,
|
||||
InstrItinData<IIC_VST, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
InstrStage<1, [A8_NLSPipe]>,
|
||||
InstrStage<1, [A8_LSPipe]>]>,
|
||||
//
|
||||
// Double-register FP Unary
|
||||
InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
|
||||
|
||||
@ -24,6 +24,8 @@ def A9_ALU1 : FuncUnit; // ALU pipeline 1
|
||||
def A9_AGU : FuncUnit; // Address generation unit for ld / st
|
||||
def A9_NPipe : FuncUnit; // NEON pipeline
|
||||
def A9_MUX0 : FuncUnit; // AGU + NEON/FPU multiplexer
|
||||
def A9_LS0 : FuncUnit; // L/S Units, 32-bit per unit. Fake FU to limit l/s.
|
||||
def A9_LS1 : FuncUnit; // L/S Units, 32-bit per unit.
|
||||
def A9_DRegsVFP: FuncUnit; // FP register set, VFP side
|
||||
def A9_DRegsN : FuncUnit; // FP register set, NEON side
|
||||
|
||||
@ -32,7 +34,7 @@ def A9_LdBypass : Bypass;
|
||||
|
||||
def CortexA9Itineraries : ProcessorItineraries<
|
||||
[A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0,
|
||||
A9_DRegsVFP, A9_DRegsN],
|
||||
A9_LS0, A9_LS1, A9_DRegsVFP, A9_DRegsN],
|
||||
[A9_LdBypass], [
|
||||
// Two fully-pipelined integer ALU pipelines
|
||||
|
||||
@ -172,87 +174,105 @@ def CortexA9Itineraries : ProcessorItineraries<
|
||||
// Immediate offset
|
||||
InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>],
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[3, 1], [A9_LdBypass]>,
|
||||
InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[4, 1], [A9_LdBypass]>,
|
||||
// FIXME: If address is 64-bit aligned, AGU cycles is 1.
|
||||
InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[3, 3, 1], [A9_LdBypass]>,
|
||||
//
|
||||
// Register offset
|
||||
InstrItinData<IIC_iLoad_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>],
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[3, 1, 1], [A9_LdBypass]>,
|
||||
InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[4, 1, 1], [A9_LdBypass]>,
|
||||
InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[3, 3, 1, 1], [A9_LdBypass]>,
|
||||
//
|
||||
// Scaled register offset
|
||||
InstrItinData<IIC_iLoad_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>],
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[4, 1, 1], [A9_LdBypass]>,
|
||||
InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[5, 1, 1], [A9_LdBypass]>,
|
||||
//
|
||||
// Immediate offset with update
|
||||
InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>],
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[3, 2, 1], [A9_LdBypass]>,
|
||||
InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[4, 3, 1], [A9_LdBypass]>,
|
||||
//
|
||||
// Register offset with update
|
||||
InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>],
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[3, 2, 1, 1], [A9_LdBypass]>,
|
||||
InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[4, 3, 1, 1], [A9_LdBypass]>,
|
||||
InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[3, 3, 1, 1], [A9_LdBypass]>,
|
||||
//
|
||||
// Scaled register offset with update
|
||||
InstrItinData<IIC_iLoad_siu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>],
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[4, 3, 1, 1], [A9_LdBypass]>,
|
||||
InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[5, 4, 1, 1], [A9_LdBypass]>,
|
||||
//
|
||||
// Load multiple, def is the 5th operand.
|
||||
// FIXME: This assumes 3 to 4 registers.
|
||||
InstrItinData<IIC_iLoad_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<2, [A9_LS0, A9_LS1]>],
|
||||
[1, 1, 1, 1, 3],
|
||||
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
|
||||
//
|
||||
// Load multiple + update, defs are the 1st and 5th operands.
|
||||
InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<2, [A9_LS0, A9_LS1]>],
|
||||
[2, 1, 1, 1, 3],
|
||||
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
|
||||
//
|
||||
@ -260,6 +280,7 @@ def CortexA9Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<2, [A9_LS0, A9_LS1]>,
|
||||
InstrStage<1, [A9_Branch]>],
|
||||
[1, 2, 1, 1, 3],
|
||||
[NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
|
||||
@ -267,7 +288,8 @@ def CortexA9Itineraries : ProcessorItineraries<
|
||||
// Pop, def is the 3rd operand.
|
||||
InstrItinData<IIC_iPop , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<2, [A9_LS0, A9_LS1]>],
|
||||
[1, 1, 3],
|
||||
[NoBypass, NoBypass, A9_LdBypass]>,
|
||||
//
|
||||
@ -275,6 +297,7 @@ def CortexA9Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_iPop_Br, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<2, [A9_LS0, A9_LS1]>,
|
||||
InstrStage<1, [A9_Branch]>],
|
||||
[1, 1, 3],
|
||||
[NoBypass, NoBypass, A9_LdBypass]>,
|
||||
@ -284,6 +307,7 @@ def CortexA9Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>,
|
||||
InstrStage<1, [A9_ALU0, A9_ALU1]>],
|
||||
[2, 1]>,
|
||||
|
||||
@ -292,75 +316,92 @@ def CortexA9Itineraries : ProcessorItineraries<
|
||||
// Immediate offset
|
||||
InstrItinData<IIC_iStore_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>], [1, 1]>,
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>], [1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>], [1, 1]>,
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>], [1, 1]>,
|
||||
// FIXME: If address is 64-bit aligned, AGU cycles is 1.
|
||||
InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>], [1, 1]>,
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>], [1, 1]>,
|
||||
//
|
||||
// Register offset
|
||||
InstrItinData<IIC_iStore_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>], [1, 1, 1]>,
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>], [1, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>], [1, 1, 1]>,
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>], [1, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>], [1, 1, 1]>,
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>], [1, 1, 1]>,
|
||||
//
|
||||
// Scaled register offset
|
||||
InstrItinData<IIC_iStore_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>], [1, 1, 1]>,
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>], [1, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>], [1, 1, 1]>,
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>], [1, 1, 1]>,
|
||||
//
|
||||
// Immediate offset with update
|
||||
InstrItinData<IIC_iStore_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>], [2, 1, 1]>,
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>], [2, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>], [3, 1, 1]>,
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>], [3, 1, 1]>,
|
||||
//
|
||||
// Register offset with update
|
||||
InstrItinData<IIC_iStore_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>],
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[2, 1, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[3, 1, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[3, 1, 1, 1]>,
|
||||
//
|
||||
// Scaled register offset with update
|
||||
InstrItinData<IIC_iStore_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>],
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[2, 1, 1, 1]>,
|
||||
InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_AGU]>],
|
||||
InstrStage<2, [A9_AGU]>,
|
||||
InstrStage<1, [A9_LS0, A9_LS1]>],
|
||||
[3, 1, 1, 1]>,
|
||||
//
|
||||
// Store multiple
|
||||
InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>]>,
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<2, [A9_LS0, A9_LS1]>]>,
|
||||
//
|
||||
// Store multiple + update
|
||||
InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_AGU]>], [2]>,
|
||||
InstrStage<1, [A9_AGU]>,
|
||||
InstrStage<2, [A9_LS0, A9_LS1]>], [2]>,
|
||||
|
||||
// Branch
|
||||
//
|
||||
@ -672,24 +713,113 @@ def CortexA9Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_NPipe]>], [2, 1, 1, 1]>,
|
||||
// NEON
|
||||
// Issue through integer pipeline, and execute in NEON unit.
|
||||
// VLD1
|
||||
// FIXME: We don't model this instruction properly
|
||||
// FIXME: Conservatively assume insufficent alignment.
|
||||
InstrItinData<IIC_VLD1, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_NPipe]>]>,
|
||||
InstrStage<2, [A9_NPipe]>],
|
||||
[2, 1]>,
|
||||
// VLD1x2
|
||||
InstrItinData<IIC_VLD1x2, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_NPipe]>],
|
||||
[2, 2, 1]>,
|
||||
// VLD1x3
|
||||
InstrItinData<IIC_VLD1x3, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<3, [A9_NPipe]>],
|
||||
[2, 2, 3, 1]>,
|
||||
// VLD1x4
|
||||
InstrItinData<IIC_VLD1x4, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<3, [A9_NPipe]>],
|
||||
[2, 2, 3, 3, 1]>,
|
||||
// VLD1u
|
||||
InstrItinData<IIC_VLD1u, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_NPipe]>],
|
||||
[2, 2, 1]>,
|
||||
// VLD1x2u
|
||||
InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_NPipe]>],
|
||||
[2, 2, 2, 1]>,
|
||||
// VLD1x3u
|
||||
InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<3, [A9_NPipe]>],
|
||||
[2, 2, 3, 2, 1]>,
|
||||
// VLD1x4u
|
||||
InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<3, [A9_NPipe]>],
|
||||
[2, 2, 3, 3, 2, 1]>,
|
||||
//
|
||||
// VLD2
|
||||
// FIXME: We don't model this instruction properly
|
||||
InstrItinData<IIC_VLD2, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
// Extra latency cycles since wbck is 6 cycles
|
||||
InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
|
||||
// Extra latency cycles since wbck is 7 cycles
|
||||
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<1, [A9_NPipe]>],
|
||||
[2, 2, 1]>,
|
||||
InstrStage<2, [A9_NPipe]>],
|
||||
[3, 3, 1]>,
|
||||
//
|
||||
// VLD2x2
|
||||
InstrItinData<IIC_VLD2x2, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<3, [A9_NPipe]>],
|
||||
[3, 4, 3, 4, 1]>,
|
||||
//
|
||||
// VLD2ln
|
||||
InstrItinData<IIC_VLD2ln, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<3, [A9_NPipe]>],
|
||||
[4, 4, 1, 1, 1, 1]>,
|
||||
//
|
||||
// VLD2u
|
||||
InstrItinData<IIC_VLD2u, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
// Extra latency cycles since wbck is 7 cycles
|
||||
InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<2, [A9_NPipe]>],
|
||||
[3, 3, 2, 1, 1, 1]>,
|
||||
//
|
||||
// VLD2x2u
|
||||
InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<3, [A9_NPipe]>],
|
||||
[3, 4, 3, 4, 2, 1]>,
|
||||
//
|
||||
// VLD2lnu
|
||||
InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A9_DRegsN], 0, Required>,
|
||||
InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
|
||||
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
|
||||
InstrStage<1, [A9_MUX0], 0>,
|
||||
InstrStage<3, [A9_NPipe]>],
|
||||
[4, 4, 2, 1, 1, 1, 1, 1]>,
|
||||
//
|
||||
// VLD3
|
||||
// FIXME: We don't model this instruction properly
|
||||
|
||||
@ -46,8 +46,8 @@ entry:
|
||||
; CHECK: t2:
|
||||
; CHECK: vld1.16
|
||||
; CHECK-NOT: vmov
|
||||
; CHECK: vld1.16
|
||||
; CHECK: vmul.i16
|
||||
; CHECK: vld1.16
|
||||
; CHECK: vmul.i16
|
||||
; CHECK-NOT: vmov
|
||||
; CHECK: vst1.16
|
||||
|
||||
Loading…
Reference in New Issue
Block a user