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Correct some load / store instruction itinerary mistakes:

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1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-10-09 01:03:04 +00:00
parent 5ed5c38423
commit d2ca813549
5 changed files with 402 additions and 305 deletions
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12
lib/Target/ARM/ARMSchedule.td
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@@ -127,7 +127,19 @@ def IIC_fpStore64 : InstrItinClass;
def IIC_fpStore_m : InstrItinClass<0>; // micro-coded
def IIC_fpStore_mu : InstrItinClass<0>; // micro-coded
def IIC_VLD1 : InstrItinClass;
def IIC_VLD1x2 : InstrItinClass;
def IIC_VLD1x3 : InstrItinClass;
def IIC_VLD1x4 : InstrItinClass;
def IIC_VLD1u : InstrItinClass;
def IIC_VLD1x2u : InstrItinClass;
def IIC_VLD1x3u : InstrItinClass;
def IIC_VLD1x4u : InstrItinClass;
def IIC_VLD2 : InstrItinClass;
def IIC_VLD2x2 : InstrItinClass;
def IIC_VLD2u : InstrItinClass;
def IIC_VLD2x2u : InstrItinClass;
def IIC_VLD2ln : InstrItinClass;
def IIC_VLD2lnu : InstrItinClass;
def IIC_VLD3 : InstrItinClass;
def IIC_VLD4 : InstrItinClass;
def IIC_VST : InstrItinClass;