6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-04 21:31:03 +00:00
Code Issues Projects Releases Wiki Activity

Fix indentation to be 2 spaces.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14512 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-06-30 22:11:03 +00:00
parent c661c3001c
commit d2d5df207a
4 changed files with 32 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/Sparc/InstSelectSimple.cpp
View File

@ -945,14 +945,14 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
case Instruction::SetGE: BranchIdx = 5; break;
}
static unsigned OpcodeTab[12] = {
// LLVM SparcV8
// unsigned signed
V8::BE, V8::BE, // seteq = be be
V8::BNE, V8::BNE, // setne = bne bne
V8::BCS, V8::BL, // setlt = bcs bl
V8::BGU, V8::BG, // setgt = bgu bg
V8::BLEU, V8::BLE, // setle = bleu ble
V8::BCC, V8::BGE // setge = bcc bge
// LLVM SparcV8
// unsigned signed
V8::BE, V8::BE, // seteq = be be
V8::BNE, V8::BNE, // setne = bne bne
V8::BCS, V8::BL, // setlt = bcs bl
V8::BGU, V8::BG, // setgt = bgu bg
V8::BLEU, V8::BLE, // setle = bleu ble
V8::BCC, V8::BGE // setge = bcc bge
};
unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];

16
lib/Target/Sparc/SparcV8ISelSimple.cpp
View File

@ -945,14 +945,14 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
case Instruction::SetGE: BranchIdx = 5; break;
}
static unsigned OpcodeTab[12] = {
// LLVM SparcV8
// unsigned signed
V8::BE, V8::BE, // seteq = be be
V8::BNE, V8::BNE, // setne = bne bne
V8::BCS, V8::BL, // setlt = bcs bl
V8::BGU, V8::BG, // setgt = bgu bg
V8::BLEU, V8::BLE, // setle = bleu ble
V8::BCC, V8::BGE // setge = bcc bge
// LLVM SparcV8
// unsigned signed
V8::BE, V8::BE, // seteq = be be
V8::BNE, V8::BNE, // setne = bne bne
V8::BCS, V8::BL, // setlt = bcs bl
V8::BGU, V8::BG, // setgt = bgu bg
V8::BLEU, V8::BLE, // setle = bleu ble
V8::BCC, V8::BGE // setge = bcc bge
};
unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];

16
lib/Target/SparcV8/InstSelectSimple.cpp
View File

@ -945,14 +945,14 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
case Instruction::SetGE: BranchIdx = 5; break;
}
static unsigned OpcodeTab[12] = {
// LLVM SparcV8
// unsigned signed
V8::BE, V8::BE, // seteq = be be
V8::BNE, V8::BNE, // setne = bne bne
V8::BCS, V8::BL, // setlt = bcs bl
V8::BGU, V8::BG, // setgt = bgu bg
V8::BLEU, V8::BLE, // setle = bleu ble
V8::BCC, V8::BGE // setge = bcc bge
// LLVM SparcV8
// unsigned signed
V8::BE, V8::BE, // seteq = be be
V8::BNE, V8::BNE, // setne = bne bne
V8::BCS, V8::BL, // setlt = bcs bl
V8::BGU, V8::BG, // setgt = bgu bg
V8::BLEU, V8::BLE, // setle = bleu ble
V8::BCC, V8::BGE // setge = bcc bge
};
unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];

16
lib/Target/SparcV8/SparcV8ISelSimple.cpp
View File

@ -945,14 +945,14 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
case Instruction::SetGE: BranchIdx = 5; break;
}
static unsigned OpcodeTab[12] = {
// LLVM SparcV8
// unsigned signed
V8::BE, V8::BE, // seteq = be be
V8::BNE, V8::BNE, // setne = bne bne
V8::BCS, V8::BL, // setlt = bcs bl
V8::BGU, V8::BG, // setgt = bgu bg
V8::BLEU, V8::BLE, // setle = bleu ble
V8::BCC, V8::BGE // setge = bcc bge
// LLVM SparcV8
// unsigned signed
V8::BE, V8::BE, // seteq = be be
V8::BNE, V8::BNE, // setne = bne bne
V8::BCS, V8::BL, // setlt = bcs bl
V8::BGU, V8::BG, // setgt = bgu bg
V8::BLEU, V8::BLE, // setle = bleu ble
V8::BCC, V8::BGE // setge = bcc bge
};
unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];