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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-25 16:24:23 +00:00
Fix indentation to be 2 spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14512 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@ -945,14 +945,14 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
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case Instruction::SetGE: BranchIdx = 5; break;
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case Instruction::SetGE: BranchIdx = 5; break;
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}
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}
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static unsigned OpcodeTab[12] = {
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static unsigned OpcodeTab[12] = {
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// LLVM SparcV8
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// LLVM SparcV8
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// unsigned signed
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// unsigned signed
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V8::BE, V8::BE, // seteq = be be
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V8::BE, V8::BE, // seteq = be be
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V8::BNE, V8::BNE, // setne = bne bne
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V8::BNE, V8::BNE, // setne = bne bne
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V8::BCS, V8::BL, // setlt = bcs bl
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V8::BCS, V8::BL, // setlt = bcs bl
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V8::BGU, V8::BG, // setgt = bgu bg
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V8::BGU, V8::BG, // setgt = bgu bg
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V8::BLEU, V8::BLE, // setle = bleu ble
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V8::BLEU, V8::BLE, // setle = bleu ble
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V8::BCC, V8::BGE // setge = bcc bge
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V8::BCC, V8::BGE // setge = bcc bge
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};
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};
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unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];
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unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];
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@ -945,14 +945,14 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
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case Instruction::SetGE: BranchIdx = 5; break;
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case Instruction::SetGE: BranchIdx = 5; break;
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}
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}
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static unsigned OpcodeTab[12] = {
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static unsigned OpcodeTab[12] = {
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// LLVM SparcV8
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// LLVM SparcV8
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// unsigned signed
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// unsigned signed
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V8::BE, V8::BE, // seteq = be be
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V8::BE, V8::BE, // seteq = be be
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V8::BNE, V8::BNE, // setne = bne bne
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V8::BNE, V8::BNE, // setne = bne bne
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V8::BCS, V8::BL, // setlt = bcs bl
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V8::BCS, V8::BL, // setlt = bcs bl
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V8::BGU, V8::BG, // setgt = bgu bg
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V8::BGU, V8::BG, // setgt = bgu bg
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V8::BLEU, V8::BLE, // setle = bleu ble
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V8::BLEU, V8::BLE, // setle = bleu ble
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V8::BCC, V8::BGE // setge = bcc bge
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V8::BCC, V8::BGE // setge = bcc bge
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};
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};
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unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];
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unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];
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@ -945,14 +945,14 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
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case Instruction::SetGE: BranchIdx = 5; break;
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case Instruction::SetGE: BranchIdx = 5; break;
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}
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}
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static unsigned OpcodeTab[12] = {
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static unsigned OpcodeTab[12] = {
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// LLVM SparcV8
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// LLVM SparcV8
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// unsigned signed
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// unsigned signed
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V8::BE, V8::BE, // seteq = be be
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V8::BE, V8::BE, // seteq = be be
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V8::BNE, V8::BNE, // setne = bne bne
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V8::BNE, V8::BNE, // setne = bne bne
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V8::BCS, V8::BL, // setlt = bcs bl
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V8::BCS, V8::BL, // setlt = bcs bl
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V8::BGU, V8::BG, // setgt = bgu bg
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V8::BGU, V8::BG, // setgt = bgu bg
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V8::BLEU, V8::BLE, // setle = bleu ble
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V8::BLEU, V8::BLE, // setle = bleu ble
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V8::BCC, V8::BGE // setge = bcc bge
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V8::BCC, V8::BGE // setge = bcc bge
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};
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};
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unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];
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unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];
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@ -945,14 +945,14 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
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case Instruction::SetGE: BranchIdx = 5; break;
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case Instruction::SetGE: BranchIdx = 5; break;
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}
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}
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static unsigned OpcodeTab[12] = {
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static unsigned OpcodeTab[12] = {
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// LLVM SparcV8
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// LLVM SparcV8
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// unsigned signed
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// unsigned signed
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V8::BE, V8::BE, // seteq = be be
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V8::BE, V8::BE, // seteq = be be
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V8::BNE, V8::BNE, // setne = bne bne
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V8::BNE, V8::BNE, // setne = bne bne
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V8::BCS, V8::BL, // setlt = bcs bl
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V8::BCS, V8::BL, // setlt = bcs bl
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V8::BGU, V8::BG, // setgt = bgu bg
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V8::BGU, V8::BG, // setgt = bgu bg
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V8::BLEU, V8::BLE, // setle = bleu ble
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V8::BLEU, V8::BLE, // setle = bleu ble
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V8::BCC, V8::BGE // setge = bcc bge
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V8::BCC, V8::BGE // setge = bcc bge
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};
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};
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unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];
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unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];
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