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[Hexagon] Relocating logical instructions and templates later in the td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223523 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
ec51bc6f3a
commit
d2f12fd27a
@ -478,121 +478,6 @@ multiclass ALU32_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
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}
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}
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//===----------------------------------------------------------------------===//
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// template class for non-predicated alu32_2op instructions
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// - aslh, asrh, sxtb, sxth, zxth
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//===----------------------------------------------------------------------===//
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let hasNewValue = 1, opNewValue = 0 in
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class T_ALU32_2op <string mnemonic, bits<3> minOp> :
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ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
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"$Rd = "#mnemonic#"($Rs)", [] > {
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bits<5> Rd;
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bits<5> Rs;
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let IClass = 0b0111;
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let Inst{27-24} = 0b0000;
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let Inst{23-21} = minOp;
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let Inst{13} = 0b0;
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let Inst{4-0} = Rd;
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let Inst{20-16} = Rs;
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}
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//===----------------------------------------------------------------------===//
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// template class for predicated alu32_2op instructions
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// - aslh, asrh, sxtb, sxth, zxtb, zxth
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, validSubTargets = HasV4SubT,
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hasNewValue = 1, opNewValue = 0 in
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class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
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bit isPredNew > :
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ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
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!if(isPredNot, "if (!$Pu", "if ($Pu")
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#!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
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bits<5> Rd;
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bits<2> Pu;
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bits<5> Rs;
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let IClass = 0b0111;
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let Inst{27-24} = 0b0000;
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let Inst{23-21} = minOp;
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let Inst{13} = 0b1;
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let Inst{11} = isPredNot;
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let Inst{10} = isPredNew;
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let Inst{4-0} = Rd;
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let Inst{9-8} = Pu;
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let Inst{20-16} = Rs;
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}
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multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
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// Predicate new
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let isPredicatedNew = 1 in
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def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
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}
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}
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multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
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let BaseOpcode = mnemonic in {
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let isPredicable = 1, hasSideEffects = 0 in
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def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
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let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
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defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
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defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
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}
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}
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}
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let isCodeGenOnly = 0 in {
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defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
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defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
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defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
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defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
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defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
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}
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// Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
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// Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
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// predicated forms while 'and' doesn't. Since integrated assembler can't
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// handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
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// immediate operand is set to '255'.
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let hasNewValue = 1, opNewValue = 0 in
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class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
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"$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
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bits<5> Rd;
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bits<5> Rs;
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bits<10> s10 = 255;
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let IClass = 0b0111;
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let Inst{27-22} = 0b011000;
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let Inst{4-0} = Rd;
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let Inst{20-16} = Rs;
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let Inst{21} = s10{9};
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let Inst{13-5} = s10{8-0};
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}
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//Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
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multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
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let BaseOpcode = mnemonic in {
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let isPredicable = 1, hasSideEffects = 0 in
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def A2_#NAME : T_ZXTB;
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let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
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defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
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defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
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}
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}
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}
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let isCodeGenOnly=0 in
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defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
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// Combines the two integer registers SRC1 and SRC2 into a double register.
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let isPredicable = 1 in
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class T_Combine : ALU32_rr<(outs DoubleRegs:$dst),
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@ -764,7 +649,6 @@ def TFCR : CRInst<(outs CRRegs:$dst), (ins IntRegs:$src1),
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//===----------------------------------------------------------------------===//
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// ALU32/PERM +
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//===----------------------------------------------------------------------===//
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// Scalar mux register immediate.
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let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
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InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
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@ -822,6 +706,121 @@ def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
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let Inst{4-0} = Rd;
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}
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//===----------------------------------------------------------------------===//
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// template class for non-predicated alu32_2op instructions
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// - aslh, asrh, sxtb, sxth, zxth
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//===----------------------------------------------------------------------===//
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let hasNewValue = 1, opNewValue = 0 in
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class T_ALU32_2op <string mnemonic, bits<3> minOp> :
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ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
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"$Rd = "#mnemonic#"($Rs)", [] > {
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bits<5> Rd;
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bits<5> Rs;
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let IClass = 0b0111;
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let Inst{27-24} = 0b0000;
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let Inst{23-21} = minOp;
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let Inst{13} = 0b0;
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let Inst{4-0} = Rd;
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let Inst{20-16} = Rs;
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}
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//===----------------------------------------------------------------------===//
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// template class for predicated alu32_2op instructions
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// - aslh, asrh, sxtb, sxth, zxtb, zxth
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, validSubTargets = HasV4SubT,
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hasNewValue = 1, opNewValue = 0 in
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class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
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bit isPredNew > :
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ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
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!if(isPredNot, "if (!$Pu", "if ($Pu")
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#!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
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bits<5> Rd;
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bits<2> Pu;
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bits<5> Rs;
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let IClass = 0b0111;
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let Inst{27-24} = 0b0000;
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let Inst{23-21} = minOp;
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let Inst{13} = 0b1;
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let Inst{11} = isPredNot;
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let Inst{10} = isPredNew;
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let Inst{4-0} = Rd;
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let Inst{9-8} = Pu;
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let Inst{20-16} = Rs;
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}
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multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
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// Predicate new
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let isPredicatedNew = 1 in
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def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
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}
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}
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multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
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let BaseOpcode = mnemonic in {
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let isPredicable = 1, hasSideEffects = 0 in
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def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
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let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
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defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
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defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
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}
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}
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}
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let isCodeGenOnly = 0 in {
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defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
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defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
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defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
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defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
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defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
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}
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// Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
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// Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
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// predicated forms while 'and' doesn't. Since integrated assembler can't
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// handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
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// immediate operand is set to '255'.
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let hasNewValue = 1, opNewValue = 0 in
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class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
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"$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255)
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bits<5> Rd;
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bits<5> Rs;
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bits<10> s10 = 255;
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let IClass = 0b0111;
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let Inst{27-22} = 0b011000;
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let Inst{4-0} = Rd;
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let Inst{20-16} = Rs;
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let Inst{21} = s10{9};
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let Inst{13-5} = s10{8-0};
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}
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//Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
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multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
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let BaseOpcode = mnemonic in {
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let isPredicable = 1, hasSideEffects = 0 in
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def A2_#NAME : T_ZXTB;
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let validSubTargets = HasV4SubT, isPredicated = 1, hasSideEffects = 0 in {
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defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
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defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
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}
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}
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}
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let isCodeGenOnly=0 in
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defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
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let hasSideEffects = 0 in
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def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
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(ins s8Imm:$src1, s8Imm:$src2),
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