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X86: Properly decode shuffle masks when the constant pool type is weird
It's possible for the constant pool entry for the shuffle mask to come from a completely different operation. This occurs when Constants have the same bit pattern but have different types. Make DecodePSHUFBMask tolerant of types which, after a bitcast, are appropriately sized vector types. This fixes PR22188. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225597 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Majnemer
parent
776673ea09
commit
d2f4460ee7
@ -13,7 +13,10 @@
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//===----------------------------------------------------------------------===//
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#include "X86ShuffleDecode.h"
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#include "llvm/Analysis/ConstantFolding.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/CodeGen/MachineValueType.h"
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//===----------------------------------------------------------------------===//
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@ -253,57 +256,64 @@ void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
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}
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}
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void DecodePSHUFBMask(const Constant *C, SmallVectorImpl<int> &ShuffleMask) {
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void DecodePSHUFBMask(const Constant *C, const DataLayout *TD,
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SmallVectorImpl<int> &ShuffleMask) {
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Type *MaskTy = C->getType();
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assert(MaskTy->isVectorTy() && "Expected a vector constant mask!");
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assert(MaskTy->getVectorElementType()->isIntegerTy(8) &&
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"Expected i8 constant mask elements!");
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int NumElements = MaskTy->getVectorNumElements();
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// It is not an error for the PSHUFB mask to not be a vector of i8 because the
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// constant pool uniques constants by their bit representation.
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// e.g. the following take up the same space in the constant pool:
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// i128 -170141183420855150465331762880109871104
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//
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// <2 x i64> <i64 -9223372034707292160, i64 -9223372034707292160>
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//
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// <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32
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// -2147483648>
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unsigned MaskTySize = MaskTy->getPrimitiveSizeInBits();
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VectorType *DestTy = nullptr;
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if (MaskTySize == 128)
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DestTy = VectorType::get(Type::getInt8Ty(MaskTy->getContext()), 16);
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else if (MaskTySize == 256)
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DestTy = VectorType::get(Type::getInt8Ty(MaskTy->getContext()), 32);
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// FIXME: Add support for AVX-512.
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assert((NumElements == 16 || NumElements == 32) &&
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"Only 128-bit and 256-bit vectors supported!");
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if (!DestTy)
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return;
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if (DestTy != MaskTy) {
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if (!CastInst::castIsValid(Instruction::BitCast, const_cast<Constant *>(C),
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DestTy))
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return;
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C = ConstantFoldInstOperands(Instruction::BitCast, DestTy,
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const_cast<Constant *>(C), TD);
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MaskTy = DestTy;
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}
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int NumElements = MaskTy->getVectorNumElements();
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ShuffleMask.reserve(NumElements);
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if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
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assert((unsigned)NumElements == CDS->getNumElements() &&
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"Constant mask has a different number of elements!");
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for (int i = 0; i < NumElements; ++i) {
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// For AVX vectors with 32 bytes the base of the shuffle is the 16-byte
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// lane of the vector we're inside.
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int Base = i < 16 ? 0 : 16;
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uint64_t Element = CDS->getElementAsInteger(i);
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// If the high bit (7) of the byte is set, the element is zeroed.
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if (Element & (1 << 7))
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ShuffleMask.push_back(SM_SentinelZero);
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else {
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// Only the least significant 4 bits of the byte are used.
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int Index = Base + (Element & 0xf);
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ShuffleMask.push_back(Index);
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}
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for (int i = 0; i < NumElements; ++i) {
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// For AVX vectors with 32 bytes the base of the shuffle is the 16-byte
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// lane of the vector we're inside.
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int Base = i < 16 ? 0 : 16;
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Constant *COp = C->getAggregateElement(i);
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if (!COp) {
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ShuffleMask.clear();
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return;
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} else if (isa<UndefValue>(COp)) {
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ShuffleMask.push_back(SM_SentinelUndef);
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continue;
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}
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} else if (auto *CV = dyn_cast<ConstantVector>(C)) {
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assert((unsigned)NumElements == CV->getNumOperands() &&
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"Constant mask has a different number of elements!");
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for (int i = 0; i < NumElements; ++i) {
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// For AVX vectors with 32 bytes the base of the shuffle is the 16-byte
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// lane of the vector we're inside.
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int Base = i < 16 ? 0 : 16;
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Constant *COp = CV->getOperand(i);
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if (isa<UndefValue>(COp)) {
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ShuffleMask.push_back(SM_SentinelUndef);
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continue;
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}
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uint64_t Element = cast<ConstantInt>(COp)->getZExtValue();
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// If the high bit (7) of the byte is set, the element is zeroed.
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if (Element & (1 << 7))
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ShuffleMask.push_back(SM_SentinelZero);
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else {
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// Only the least significant 4 bits of the byte are used.
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int Index = Base + (Element & 0xf);
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ShuffleMask.push_back(Index);
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}
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uint64_t Element = cast<ConstantInt>(COp)->getZExtValue();
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// If the high bit (7) of the byte is set, the element is zeroed.
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if (Element & (1 << 7))
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ShuffleMask.push_back(SM_SentinelZero);
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else {
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// Only the least significant 4 bits of the byte are used.
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int Index = Base + (Element & 0xf);
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ShuffleMask.push_back(Index);
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}
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}
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}
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@ -24,6 +24,7 @@
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namespace llvm {
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class Constant;
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class DataLayout;
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class MVT;
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enum { SM_SentinelUndef = -1, SM_SentinelZero = -2 };
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@ -68,7 +69,8 @@ void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
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void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a PSHUFB mask from an IR-level vector constant.
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void DecodePSHUFBMask(const Constant *C, SmallVectorImpl<int> &ShuffleMask);
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void DecodePSHUFBMask(const Constant *C, const DataLayout *TD,
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SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a PSHUFB mask from a raw array of constants such as from
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/// BUILD_VECTOR.
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@ -5365,7 +5365,7 @@ static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
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/// IsUnary to true if only uses one source. Note that this will set IsUnary for
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/// shuffles which use a single input multiple times, and in those cases it will
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/// adjust the mask to only have indices within that single input.
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static bool getTargetShuffleMask(SDNode *N, MVT VT,
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static bool getTargetShuffleMask(SDNode *N, MVT VT, const DataLayout *TD,
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SmallVectorImpl<int> &Mask, bool &IsUnary) {
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unsigned NumElems = VT.getVectorNumElements();
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SDValue ImmN;
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@ -5472,13 +5472,7 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT,
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return false;
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if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
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// FIXME: Support AVX-512 here.
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Type *Ty = C->getType();
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if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
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Ty->getVectorNumElements() != 32))
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return false;
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DecodePSHUFBMask(C, Mask);
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DecodePSHUFBMask(C, TD, Mask);
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break;
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}
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@ -5541,6 +5535,7 @@ static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
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SDValue V = SDValue(N, 0);
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EVT VT = V.getValueType();
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unsigned Opcode = V.getOpcode();
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const DataLayout *TD = DAG.getSubtarget().getDataLayout();
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// Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
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if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
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@ -5562,7 +5557,7 @@ static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
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SmallVector<int, 16> ShuffleMask;
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bool IsUnary;
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if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
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if (!getTargetShuffleMask(N, ShufVT, TD, ShuffleMask, IsUnary))
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return SDValue();
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int Elt = ShuffleMask[Index];
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@ -22117,7 +22112,8 @@ static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
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return false;
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SmallVector<int, 16> OpMask;
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bool IsUnary;
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bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
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bool HaveMask = getTargetShuffleMask(
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Op.getNode(), VT, Subtarget->getDataLayout(), OpMask, IsUnary);
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// We only can combine unary shuffles which we can decode the mask for.
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if (!HaveMask || !IsUnary)
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return false;
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@ -22208,10 +22204,12 @@ static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
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///
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/// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
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/// PSHUF-style masks that can be reused with such instructions.
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static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
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static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N,
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const DataLayout *TD) {
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SmallVector<int, 4> Mask;
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bool IsUnary;
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bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
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bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), TD,
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Mask, IsUnary);
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(void)HaveMask;
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assert(HaveMask);
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@ -22243,6 +22241,7 @@ combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
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assert(N.getOpcode() == X86ISD::PSHUFD &&
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"Called with something other than an x86 128-bit half shuffle!");
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SDLoc DL(N);
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const DataLayout *TD = DAG.getSubtarget().getDataLayout();
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// Walk up a single-use chain looking for a combinable shuffle. Keep a stack
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// of the shuffles in the chain so that we can form a fresh chain to replace
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@ -22328,7 +22327,7 @@ combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
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return SDValue();
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// Merge this node's mask and our incoming mask.
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SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
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SmallVector<int, 4> VMask = getPSHUFShuffleMask(V, TD);
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for (int &M : Mask)
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M = VMask[M];
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V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
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@ -22377,6 +22376,7 @@ static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
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"Called with something other than an x86 128-bit half shuffle!");
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SDLoc DL(N);
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unsigned CombineOpcode = N.getOpcode();
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const DataLayout *TD = DAG.getSubtarget().getDataLayout();
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// Walk up a single-use chain looking for a combinable shuffle.
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SDValue V = N.getOperand(0);
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@ -22415,7 +22415,7 @@ static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
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// Merge this node's mask and our incoming mask (adjusted to account for all
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// the pshufd instructions encountered).
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SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
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SmallVector<int, 4> VMask = getPSHUFShuffleMask(V, TD);
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for (int &M : Mask)
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M = VMask[M];
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V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
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@ -22437,13 +22437,14 @@ static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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SDLoc DL(N);
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MVT VT = N.getSimpleValueType();
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const DataLayout *TD = Subtarget->getDataLayout();
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SmallVector<int, 4> Mask;
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switch (N.getOpcode()) {
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case X86ISD::PSHUFD:
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case X86ISD::PSHUFLW:
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case X86ISD::PSHUFHW:
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Mask = getPSHUFShuffleMask(N);
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Mask = getPSHUFShuffleMask(N, TD);
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assert(Mask.size() == 4);
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break;
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default:
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@ -22495,8 +22496,8 @@ static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
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while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
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D = D.getOperand(0);
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if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
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SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
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SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
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SmallVector<int, 4> VMask = getPSHUFShuffleMask(V, TD);
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SmallVector<int, 4> DMask = getPSHUFShuffleMask(D, TD);
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int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
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int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
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int WordMask[8];
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@ -22749,9 +22750,10 @@ static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
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if (!InVec.hasOneUse())
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return SDValue();
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const DataLayout *TD = DAG.getSubtarget().getDataLayout();
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SmallVector<int, 16> ShuffleMask;
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bool UnaryShuffle;
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if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
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if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(), TD,
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ShuffleMask, UnaryShuffle))
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return SDValue();
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@ -1161,7 +1161,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
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if (auto *C = getConstantFromPool(*MI, MaskOp)) {
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SmallVector<int, 16> Mask;
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DecodePSHUFBMask(C, Mask);
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DecodePSHUFBMask(C, TM.getSubtargetImpl()->getDataLayout(), Mask);
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if (!Mask.empty())
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OutStreamer.AddComment(getShuffleComment(DstOp, SrcOp, Mask));
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}
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@ -27,4 +27,14 @@ define <16 x i8> @test3(<16 x i8> %V) {
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ret <16 x i8> %1
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}
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; Test that we won't crash when the constant was reused for another instruction.
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define <16 x i8> @test4(<2 x i64>* %V) {
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; CHECK-LABEL: test4
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; CHECK: pshufb {{.*}}# xmm0 = xmm0[8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7]
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store <2 x i64> <i64 1084818905618843912, i64 506097522914230528>, <2 x i64>* %V, align 16
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%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> undef, <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
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ret <16 x i8> %1
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}
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declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
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