6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 04:30:23 +00:00
Code Issues Projects Releases Wiki Activity

Avoid redundant select node in early if-conversion pass

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240072 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Yi Jiang 2015-06-18 22:34:09 +00:00
parent 5caacef5c1
commit d30c2356b0
2 changed files with 54 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/CodeGen/EarlyIfConversion.cpp
View File

@ -479,11 +479,20 @@ void SSAIfConv::rewritePHIOperands() {
// Convert all PHIs to select instructions inserted before FirstTerm.
for (unsigned i = 0, e = PHIs.size(); i != e; ++i) {
PHIInfo &PI = PHIs[i];
unsigned DstReg = 0;
DEBUG(dbgs() << "If-converting " << *PI.PHI);
unsigned PHIDst = PI.PHI->getOperand(0).getReg();
unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
if (PI.TReg == PI.FReg) {
// We do not need the select instruction if both incoming values are
// equal.
DstReg = PI.TReg;
} else {
unsigned PHIDst = PI.PHI->getOperand(0).getReg();
DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
TII->insertSelect(*Head, FirstTerm, HeadDL,
DstReg, Cond, PI.TReg, PI.FReg);
DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
}
// Rewrite PHI operands TPred -> (DstReg, Head), remove FPred.
for (unsigned i = PI.PHI->getNumOperands(); i != 1; i -= 2) {

41
test/CodeGen/AArch64/ifcvt-select.ll Normal file
View File

@ -0,0 +1,41 @@
; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
; Do not generate redundant select in early if-converstion pass.
define i32 @foo(i32 %a, i32 %b) {
entry:
;CHECK-LABEL: foo:
;CHECK: csinc
;CHECK-NOT: csel
%sub = sub nsw i32 %b, %a
%cmp10 = icmp sgt i32 %a, 0
br i1 %cmp10, label %while.body.lr.ph, label %while.end
while.body.lr.ph:
br label %while.body
while.body:
%j.012 = phi i32 [ %sub, %while.body.lr.ph ], [ %inc, %if.then ], [ %inc, %if.else ]
%i.011 = phi i32 [ %a, %while.body.lr.ph ], [ %inc2, %if.then ], [ %dec, %if.else ]
%cmp1 = icmp slt i32 %i.011, %j.012
br i1 %cmp1, label %while.end, label %while.cond
while.cond:
%inc = add nsw i32 %j.012, 5
%cmp2 = icmp slt i32 %inc, %b
br i1 %cmp2, label %if.then, label %if.else
if.then:
%inc2 = add nsw i32 %i.011, 1
br label %while.body
if.else:
%dec = add nsw i32 %i.011, -1
br label %while.body
while.end:
%j.0.lcssa = phi i32 [ %j.012, %while.body ], [ %sub, %entry ]
%i.0.lcssa = phi i32 [ %i.011, %while.body ], [ %a, %entry ]
%add = add nsw i32 %j.0.lcssa, %i.0.lcssa
ret i32 %add
}