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[mips][microMIPSr6] Implement mips32 to microMIPSr6 mapping support

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Differential Revision: http://reviews.llvm.org/D8661


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235505 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2015-04-22 13:27:34 +00:00
parent 61ffda59f9
commit d311051513
2 changed files with 24 additions and 3 deletions
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13
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
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@ -179,13 +179,20 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
(Opcode != Mips::SLL_MM) && !Binary)
llvm_unreachable("unimplemented opcode in EncodeInstruction()");
int NewOpcode = -1;
if (isMicroMips(STI)) {
int NewOpcode = isMips32r6(STI) ?
Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6) :
Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
if (isMips32r6(STI)) {
NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
if (NewOpcode == -1)
NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
}
else
NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
if (NewOpcode != -1) {
if (Fixups.size() > N)
Fixups.pop_back();
Opcode = NewOpcode;
TmpInst.setOpcode (NewOpcode);
Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);

14
lib/Target/Mips/MipsInstrFormats.td
View File

@ -50,6 +50,20 @@ def Std2MicroMips : InstrMapping {
let ValueCols = [["se"], ["micromips"]];
}
class StdMMR6Rel;
def Std2MicroMipsR6 : InstrMapping {
let FilterClass = "StdMMR6Rel";
// Instructions with the same BaseOpcode and isNVStore values form a row.
let RowFields = ["BaseOpcode"];
// Instructions with the same predicate sense form a column.
let ColFields = ["Arch"];
// The key column is the unpredicated instructions.
let KeyCol = ["se"];
// Value columns are PredSense=true and PredSense=false
let ValueCols = [["se"], ["micromipsr6"]];
}
class StdArch {
string Arch = "se";
}