mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-05 13:26:55 +00:00
Improve the widening of integral binary vector operations
- split WidenVecRes_Binary into WidenVecRes_Binary and WidenVecRes_BinaryCanTrap - WidenVecRes_BinaryCanTrap preserves the original behaviour for operations that can trap - WidenVecRes_Binary simply widens the operation and improves codegen for 3-element vectors by allowing widening and promotion on x86 (matches the behaviour of unary and ternary operation widening) - use WidenVecRes_Binary for operations on integers. Reviewed by: nrotem git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188699 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -73,9 +73,7 @@ define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) {
|
||||
; CHECK: add3i16
|
||||
%i16vec3 = type <3 x i16>
|
||||
define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind {
|
||||
; CHECK: addl
|
||||
; CHECK: addl
|
||||
; CHECK: addl
|
||||
; CHECK: paddd
|
||||
; CHECK: ret
|
||||
%a = load %i16vec3* %ap, align 16
|
||||
%b = load %i16vec3* %bp, align 16
|
||||
@@ -135,9 +133,7 @@ define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18*
|
||||
; CHECK: add3i8
|
||||
%i8vec3 = type <3 x i8>
|
||||
define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind {
|
||||
; CHECK: addb
|
||||
; CHECK: addb
|
||||
; CHECK: addb
|
||||
; CHECK: paddd
|
||||
; CHECK: ret
|
||||
%a = load %i8vec3* %ap, align 16
|
||||
%b = load %i8vec3* %bp, align 16
|
||||
|
Reference in New Issue
Block a user