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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
* Changed Bcc instructions to behave like BPcc instructions
* BPA and BPN do not take a %cc register as a parameter * SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions * Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit * Added WRCCR{r,i} opcodes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6655 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -121,6 +121,7 @@ set op2 = 0b101 in {
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#endif
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// Section A.6: Branch on Integer condition codes (Bicc) - p146
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#if 0 // instead of using deprecated version, use the predicted version below
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set isDeprecated = 1 in {
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set op2 = 0b010 in {
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def BA : F2_2<0b1000, "ba">; // Branch always
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@ -141,6 +142,29 @@ set isDeprecated = 1 in {
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def BVS : F2_2<0b0111, "bvs">; // Branch on overflow set
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}
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}
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#endif
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// Using the format of A.7 instructions...
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set op2 = 0b001 in {
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set cc = 0 in { // BA and BN don't read condition codes
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def BA : F2_3<0b1000, "ba">; // Branch always
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def BN : F2_3<0b0000, "bn">; // Branch never
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}
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def BNE : F2_3<0b1001, "bne">; // Branch !=
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def BE : F2_3<0b0001, "be">; // Branch ==
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def BG : F2_3<0b1010, "bg">; // Branch >
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def BLE : F2_3<0b0010, "ble">; // Branch <=
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def BGE : F2_3<0b1011, "bge">; // Branch >=
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def BL : F2_3<0b0011, "bl">; // Branch <
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def BGU : F2_3<0b1100, "bgu">; // Branch unsigned >
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def BLEU : F2_3<0b0100, "bleu">; // Branch unsigned <=
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def BCC : F2_3<0b1101, "bcc">; // Branch unsigned >=
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def BCS : F2_3<0b0101, "bcs">; // Branch unsigned <=
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def BPOS : F2_3<0b1110, "bpos">; // Branch on positive
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def BNEG : F2_3<0b0110, "bneg">; // Branch on negative
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def BVC : F2_3<0b1111, "bvc">; // Branch on overflow clear
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def BVS : F2_3<0b0111, "bvs">; // Branch on overflow set
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}
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// Section A.7: Branch on integer condition codes with prediction - p148
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// Not used in the Sparc backend
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@ -669,28 +693,20 @@ set x = 0 in {
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#endif
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// uses 6 least significant bits of rs2
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set x = 0 in {
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def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
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def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r
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def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r
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}
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set x = 1 in {
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def SLLr6 : F3_11<2, 0b100101, "sll">; // sll r, r, r
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def SRLr6 : F3_11<2, 0b100110, "srl">; // srl r, r, r
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def SRAr6 : F3_11<2, 0b100111, "sra">; // sra r, r, r
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def SLLXr6 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
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def SRLXr6 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
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def SRAXr6 : F3_11<2, 0b100111, "srax">; // srax r, r, r
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}
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// Not currently used in the Sparc backend
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#if 0
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def SLLi5 : F3_12<2, 0b100101, "sll">; // sll r, shcnt32, r
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def SRLi5 : F3_12<2, 0b100110, "srl">; // srl r, shcnt32, r
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def SRAi5 : F3_12<2, 0b100111, "sra">; // sra r, shcnt32, r
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def SLLXi5 : F3_12<2, 0b100101, "sllx">; // sllx r, shcnt32, r
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def SRLXi5 : F3_12<2, 0b100110, "srlx">; // srlx r, shcnt32, r
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def SRAXi5 : F3_12<2, 0b100111, "srax">; // srax r, shcnt32, r
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#endif
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def SLLi6 : F3_13<2, 0b100101, "sll">; // sll r, shcnt64, r
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def SRLi6 : F3_13<2, 0b100110, "srl">; // srl r, shcnt64, r
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def SRAi6 : F3_13<2, 0b100111, "sra">; // sra r, shcnt64, r
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def SLLXi6 : F3_13<2, 0b100101, "sllx">; // sllx r, shcnt64, r
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def SRLXi6 : F3_13<2, 0b100110, "srlx">; // srlx r, shcnt64, r
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def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
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@ -754,3 +770,9 @@ def SUBCccr : F3_1<2, 0b011100, "subccc">; // subccc r, r, r
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def SUBCcci : F3_2<2, 0b011100, "subccc">; // subccc r, i, r
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// FIXME: More...?
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// Section A.63: Write State Register - p244
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set rd = 2 in {
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def WRCCRr : F3_1<2, 0b110000, "wr">; // wr r, r, %y/ccr/etc
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def WRCCRi : F3_2<2, 0b110000, "wr">; // wr r, i, %y/ccr/etc
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}
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@ -135,12 +135,12 @@ I(XNORccr, "xnorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICA
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I(XNORcci, "xnorcc", 4, 2, B12, true , 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG)
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// Shift operations
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I(SLLr6 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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I(SLLi6 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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I(SRLr6 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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I(SRLi6 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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I(SRAr6 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG)
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I(SRAi6 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG)
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I(SLLr5 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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I(SLLi5 , "sll", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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I(SRLr5 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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I(SRLi5 , "srl", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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I(SRAr5 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG)
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I(SRAi5 , "sra", 3, 2, B5, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG)
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I(SLLXr6, "sllx", 3, 2, B6, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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I(SLLXi6, "sllx", 3, 2, B6, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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I(SRLXr6, "srlx", 3, 2, B6, true , 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG)
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@ -526,7 +526,8 @@ I(RESTOREi, "restore", 3, 2, B12, true , 0, 1, SPARC_SINGLE, M_INT_FLAG | M_AR
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// Read and Write CCR register from/to an int reg
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I(RDCCR, "rd", 2, 2, 0, false, 0, 1, SPARC_SINGLE, M_INT_FLAG | M_CC_FLAG)
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I(WRCCR, "wr", 2, 2, 0, false, 0, 1, SPARC_SINGLE, M_INT_FLAG | M_CC_FLAG)
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I(WRCCRr, "wr", 2, 2, 0, false, 0, 1, SPARC_SINGLE, M_INT_FLAG | M_CC_FLAG)
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I(WRCCRi, "wr", 2, 2, 0, false, 0, 1, SPARC_SINGLE, M_INT_FLAG | M_CC_FLAG)
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// Synthetic phi operation for near-SSA form of machine code
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// Number of operands is variable, indicated by -1. Result is the first op.
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@ -145,7 +145,7 @@ CreateSETSWConst(const TargetMachine& target, int32_t C,
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// Sign-extend to the high 32 bits if needed.
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// NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
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if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
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mvec.push_back(BuildMI(V9::SRAi6, 3).addReg(dest).addZImm(0).addRegDef(dest));
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mvec.push_back(BuildMI(V9::SRAi5,3).addReg(dest).addZImm(0).addRegDef(dest));
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}
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@ -692,7 +692,7 @@ CreateBitExtensionInstructions(bool signExtend,
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srcVal = tmpI;
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}
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mvec.push_back(BuildMI(signExtend? V9::SRAi6 : V9::SRLi6, 3)
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mvec.push_back(BuildMI(signExtend? V9::SRAi5 : V9::SRLi5, 3)
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.addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
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}
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@ -747,7 +747,7 @@ CreateShiftInstructions(const TargetMachine& target,
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Value* shiftDest = destVal;
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unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
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if ((shiftOpCode == V9::SLLr6 || shiftOpCode == V9::SLLXr6) && opSize < 8) {
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if ((shiftOpCode == V9::SLLr5 || shiftOpCode == V9::SLLXr6) && opSize < 8) {
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// put SLL result into a temporary
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shiftDest = new TmpInstruction(mcfi, argVal1, optArgVal2, "sllTmp");
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}
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@ -815,7 +815,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
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mvec.push_back(M);
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} else if (isPowerOf2(C, pow)) {
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unsigned opSize = target.getTargetData().getTypeSize(resultType);
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MachineOpCode opCode = (opSize <= 32)? V9::SLLr6 : V9::SLLXr6;
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MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
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CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
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destVal, mvec, mcfi);
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}
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@ -979,7 +979,7 @@ CreateDivConstInstruction(TargetMachine &target,
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// Create the SRL or SRLX instruction to get the sign bit
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mvec.push_back(BuildMI((resultType==Type::LongTy) ?
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V9::SRLXi6 : V9::SRLi6, 3)
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V9::SRLXi6 : V9::SRLi5, 3)
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.addReg(LHS)
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.addSImm((resultType==Type::LongTy)? 63 : 31)
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.addRegDef(srlTmp));
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@ -990,11 +990,11 @@ CreateDivConstInstruction(TargetMachine &target,
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// Get the shift operand and "right-shift" opcode to do the divide
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shiftOperand = addTmp;
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opCode = (resultType==Type::LongTy) ? V9::SRAXi6 : V9::SRAi6;
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opCode = (resultType==Type::LongTy) ? V9::SRAXi6 : V9::SRAi5;
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} else {
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// Get the shift operand and "right-shift" opcode to do the divide
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shiftOperand = LHS;
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opCode = (resultType==Type::LongTy) ? V9::SRLXi6 : V9::SRLi6;
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opCode = (resultType==Type::LongTy) ? V9::SRLXi6 : V9::SRLi5;
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}
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// Now do the actual shift!
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@ -2419,7 +2419,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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"Shl unsupported for other types");
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CreateShiftInstructions(target, shlInstr->getParent()->getParent(),
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(opType == Type::LongTy)? V9::SLLXr6:V9::SLLr6,
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(opType == Type::LongTy)? V9::SLLXr6:V9::SLLr5,
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argVal1, argVal2, 0, shlInstr, mvec,
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MachineCodeForInstruction::get(shlInstr));
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break;
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@ -2431,8 +2431,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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assert((opType->isInteger() || isa<PointerType>(opType)) &&
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"Shr unsupported for other types");
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Add3OperandInstr(opType->isSigned()
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? (opType == Type::LongTy ? V9::SRAXr6 : V9::SRAr6)
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: (opType == Type::LongTy ? V9::SRLXr6 : V9::SRLr6),
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? (opType == Type::LongTy ? V9::SRAXr6 : V9::SRAr5)
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: (opType == Type::LongTy ? V9::SRLXr6 : V9::SRLr5),
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subtreeRoot, mvec);
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break;
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}
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@ -2503,7 +2503,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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for (unsigned i=0, N=mvec.size(); i < N; ++i)
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mvec[i]->substituteValue(dest, tmpI);
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M = BuildMI(V9::SRLi6, 3).addReg(tmpI).addZImm(8*(4-destSize))
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M = BuildMI(V9::SRLi5, 3).addReg(tmpI).addZImm(8*(4-destSize))
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.addReg(dest, MOTy::Def);
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mvec.push_back(M);
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} else if (destSize < 8) {
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@ -110,9 +110,9 @@ convertOpcodeFromRegToImm(unsigned Opcode) {
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case V9::XNORccr: return V9::XNORcci;
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/* shift */
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case V9::SLLr6: return V9::SLLi6;
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case V9::SRLr6: return V9::SRLi6;
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case V9::SRAr6: return V9::SRAi6;
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case V9::SLLr5: return V9::SLLi5;
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case V9::SRLr5: return V9::SRLi5;
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case V9::SRAr5: return V9::SRAi5;
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case V9::SLLXr6: return V9::SLLXi6;
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case V9::SRLXr6: return V9::SRLXi6;
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case V9::SRAXr6: return V9::SRAXi6;
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@ -86,7 +86,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
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M->setOperandLo32(1);
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mvec.push_back(M);
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M = BuildMI(V9::SRAi6, 3).addMReg(uregNum).addZImm(0)
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M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
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.addMReg(uregNum, MOTy::Def);
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mvec.push_back(M);
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@ -1068,7 +1068,8 @@ UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
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unsigned SrcReg,
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unsigned DestReg,
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int RegType) const {
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assert( ((int)SrcReg != getInvalidRegNum()) && ((int)DestReg != getInvalidRegNum()) &&
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assert( ((int)SrcReg != getInvalidRegNum()) &&
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((int)DestReg != getInvalidRegNum()) &&
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"Invalid Register");
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MachineInstr * MI = NULL;
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@ -1085,7 +1086,8 @@ UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
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// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
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assert(getRegType(SrcReg) == IntRegType
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&& "Can only copy CC reg to/from integer reg");
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MI = BuildMI(V9::WRCCR, 2).addMReg(SrcReg).addMReg(DestReg+1, MOTy::Def);
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MI = BuildMI(V9::WRCCRr, 2).addMReg(SrcReg)
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.addMReg(SparcIntRegClass::g0).addMReg(DestReg+1, MOTy::Def);
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}
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break;
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@ -1212,7 +1214,8 @@ UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
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cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
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// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
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MI = BuildMI(V9::WRCCR, 2).addMReg(scratchReg).addMReg(DestReg+1,MOTy::Def);
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MI = BuildMI(V9::WRCCRr, 2).addMReg(scratchReg)
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.addMReg(SparcIntRegClass::g0).addMReg(DestReg+1,MOTy::Def);
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break;
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case FloatCCRegType: {
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