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misched: add DAG edges from vreg defs to ExitSU.

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These edges are not really necessary, but it is consistent with the
way we currently create physreg edges. Scheduler heuristics that
expect a DAG edge to the block terminator could benefit from this
change. Although in the future I hope we have a better mechanism for
modeling latency across scheduling regions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152895 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-03-16 05:04:25 +00:00
parent 75ae20366f
commit d3a7486ef3
1 changed files with 3 additions and 1 deletions
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4
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -201,8 +201,10 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() {
if (TRI->isPhysicalRegister(Reg))
Uses[Reg].push_back(&ExitSU);
else
else {
assert(!IsPostRA && "Virtual register encountered after regalloc.");
addVRegUseDeps(&ExitSU, i);
}
}
} else {
// For others, e.g. fallthrough, conditional branch, assume the exit