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R600/SI: add post ISel folding for SI v2
Include immediate folding and SGPR limit handling for VOP3 instructions. v2: remove leftover hasExtraSrcRegAllocReq Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176101 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig
parent
c018ecac2f
commit
d3b5509b80
@ -16,6 +16,7 @@
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#include "AMDGPURegisterInfo.h"
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#include "AMDILDevices.h"
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#include "R600InstrInfo.h"
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#include "SIISelLowering.h"
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#include "llvm/ADT/ValueMap.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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@ -26,7 +26,8 @@ using namespace llvm;
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SITargetLowering::SITargetLowering(TargetMachine &TM) :
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AMDGPUTargetLowering(TM),
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TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())) {
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TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())),
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TRI(TM.getRegisterInfo()) {
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addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
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addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
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addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
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@ -358,8 +359,206 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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return SDValue();
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}
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/// \brief Test if RegClass is one of the VSrc classes
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static bool isVSrc(unsigned RegClass) {
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return AMDGPU::VSrc_32RegClassID == RegClass ||
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AMDGPU::VSrc_64RegClassID == RegClass;
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}
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/// \brief Test if RegClass is one of the SSrc classes
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static bool isSSrc(unsigned RegClass) {
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return AMDGPU::SSrc_32RegClassID == RegClass ||
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AMDGPU::SSrc_64RegClassID == RegClass;
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}
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/// \brief Analyze the possible immediate value Op
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///
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/// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
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/// and the immediate value if it's a literal immediate
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int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
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union {
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int32_t I;
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float F;
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} Imm;
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if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N))
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Imm.I = Node->getSExtValue();
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else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
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Imm.F = Node->getValueAPF().convertToFloat();
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else
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return -1; // It isn't an immediate
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if ((Imm.I >= -16 && Imm.I <= 64) ||
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Imm.F == 0.5f || Imm.F == -0.5f ||
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Imm.F == 1.0f || Imm.F == -1.0f ||
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Imm.F == 2.0f || Imm.F == -2.0f ||
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Imm.F == 4.0f || Imm.F == -4.0f)
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return 0; // It's an inline immediate
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return Imm.I; // It's a literal immediate
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}
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/// \brief Try to fold an immediate directly into an instruction
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bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
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bool &ScalarSlotUsed) const {
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MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
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if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
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return false;
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const SDValue &Op = Mov->getOperand(0);
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int32_t Value = analyzeImmediate(Op.getNode());
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if (Value == -1) {
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// Not an immediate at all
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return false;
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} else if (Value == 0) {
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// Inline immediates can always be fold
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Operand = Op;
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return true;
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} else if (Value == Immediate) {
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// Already fold literal immediate
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Operand = Op;
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return true;
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} else if (!ScalarSlotUsed && !Immediate) {
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// Fold this literal immediate
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ScalarSlotUsed = true;
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Immediate = Value;
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Operand = Op;
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return true;
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}
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return false;
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}
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/// \brief Does "Op" fit into register class "RegClass" ?
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bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op,
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unsigned RegClass) const {
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MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
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SDNode *Node = Op.getNode();
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int OpClass;
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if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
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const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
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OpClass = Desc.OpInfo[Op.getResNo()].RegClass;
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} else if (Node->getOpcode() == ISD::CopyFromReg) {
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RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode());
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OpClass = MRI.getRegClass(Reg->getReg())->getID();
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} else
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return false;
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if (OpClass == -1)
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return false;
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return TRI->getRegClass(RegClass)->hasSubClassEq(TRI->getRegClass(OpClass));
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}
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/// \brief Make sure that we don't exeed the number of allowed scalars
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void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
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unsigned RegClass,
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bool &ScalarSlotUsed) const {
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// First map the operands register class to a destination class
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if (RegClass == AMDGPU::VSrc_32RegClassID)
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RegClass = AMDGPU::VReg_32RegClassID;
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else if (RegClass == AMDGPU::VSrc_64RegClassID)
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RegClass = AMDGPU::VReg_64RegClassID;
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else
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return;
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// Nothing todo if they fit naturaly
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if (fitsRegClass(DAG, Operand, RegClass))
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return;
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// If the scalar slot isn't used yet use it now
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if (!ScalarSlotUsed) {
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ScalarSlotUsed = true;
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return;
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}
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// This is a conservative aproach, it is possible that we can't determine
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// the correct register class and copy too often, but better save than sorry.
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SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
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SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DebugLoc(),
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Operand.getValueType(), Operand, RC);
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Operand = SDValue(Node, 0);
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}
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SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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SelectionDAG &DAG) const {
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// TODO: Implement immediate folding
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return Node;
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// Original encoding (either e32 or e64)
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int Opcode = Node->getMachineOpcode();
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const MCInstrDesc *Desc = &TII->get(Opcode);
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unsigned NumDefs = Desc->getNumDefs();
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unsigned NumOps = Desc->getNumOperands();
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int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
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bool HaveVSrc = false, HaveSSrc = false;
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// First figure out what we alread have in this instruction
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for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
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i != e && Op < NumOps; ++i, ++Op) {
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unsigned RegClass = Desc->OpInfo[Op].RegClass;
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if (isVSrc(RegClass))
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HaveVSrc = true;
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else if (isSSrc(RegClass))
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HaveSSrc = true;
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else
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continue;
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int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
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if (Imm != -1 && Imm != 0) {
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// Literal immediate
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Immediate = Imm;
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}
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}
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// If we neither have VSrc nor SSrc it makes no sense to continue
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if (!HaveVSrc && !HaveSSrc)
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return Node;
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// No scalar allowed when we have both VSrc and SSrc
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bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
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// Second go over the operands and try to fold them
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std::vector<SDValue> Ops;
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for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
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i != e && Op < NumOps; ++i, ++Op) {
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const SDValue &Operand = Node->getOperand(i);
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Ops.push_back(Operand);
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// Already folded immediate ?
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if (isa<ConstantSDNode>(Operand.getNode()) ||
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isa<ConstantFPSDNode>(Operand.getNode()))
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continue;
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// Is this a VSrc or SSrc operand ?
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unsigned RegClass = Desc->OpInfo[Op].RegClass;
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if (!isVSrc(RegClass) && !isSSrc(RegClass))
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continue;
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// Try to fold the immediates
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if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
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// Folding didn't worked, make sure we don't hit the SReg limit
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ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
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}
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}
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// Add optional chain and glue
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for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
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Ops.push_back(Node->getOperand(i));
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// Update the instruction parameters
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return DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
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}
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@ -22,6 +22,7 @@ namespace llvm {
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class SITargetLowering : public AMDGPUTargetLowering {
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const SIInstrInfo * TII;
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const TargetRegisterInfo * TRI;
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void LowerMOV_IMM(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, unsigned Opocde) const;
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@ -34,6 +35,12 @@ class SITargetLowering : public AMDGPUTargetLowering {
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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bool foldImm(SDValue &Operand, int32_t &Immediate,
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bool &ScalarSlotUsed) const;
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bool fitsRegClass(SelectionDAG &DAG, SDValue &Op, unsigned RegClass) const;
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void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
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unsigned RegClass, bool &ScalarSlotUsed) const;
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public:
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SITargetLowering(TargetMachine &tm);
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virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
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@ -42,6 +49,8 @@ public:
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const;
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int32_t analyzeImmediate(const SDNode *N) const;
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};
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} // End namespace llvm
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@ -40,11 +40,10 @@ def IMM12bit : ImmLeaf <
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[{return isUInt<12>(Imm);}]
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>;
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class InlineImm <ValueType vt> : ImmLeaf <vt, [{
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return -16 <= Imm && Imm <= 64;
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class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
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return ((const SITargetLowering &)TLI).analyzeImmediate(N) == 0;
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}]>;
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//===----------------------------------------------------------------------===//
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// SI assembler operands
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//===----------------------------------------------------------------------===//
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@ -181,7 +180,7 @@ multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
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def _e64 : VOP3 <
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{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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(outs vrc:$dst),
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(ins arc:$src0, vrc:$src1,
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(ins arc:$src0, arc:$src1,
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i32imm:$abs, i32imm:$clamp,
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i32imm:$omod, i32imm:$neg),
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opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
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@ -206,7 +205,7 @@ multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern> {
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def _e64 : VOP3b <
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{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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(outs VReg_32:$dst),
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(ins VSrc_32:$src0, VReg_32:$src1,
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(ins VSrc_32:$src0, VSrc_32:$src1,
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i32imm:$abs, i32imm:$clamp,
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i32imm:$omod, i32imm:$neg),
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opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
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@ -230,12 +229,12 @@ multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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def _e64 : VOP3 <
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{0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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(outs SReg_64:$dst),
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(ins arc:$src0, vrc:$src1,
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(ins arc:$src0, arc:$src1,
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InstFlag:$abs, InstFlag:$clamp,
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InstFlag:$omod, InstFlag:$neg),
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opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg",
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!if(!eq(!cast<string>(cond), "COND_NULL"), []<dag>,
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[(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), vrc:$src1, cond)))]
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[(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))]
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)
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> {
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let SRC2 = SIOperand.ZERO;
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@ -252,14 +251,14 @@ multiclass VOPC_64 <bits<8> op, string opName,
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class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
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op, (outs VReg_32:$dst),
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(ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2,
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(ins VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
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i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg),
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opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
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>;
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class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
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op, (outs VReg_64:$dst),
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(ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2,
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(ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2,
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i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg),
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opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
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>;
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@ -732,17 +732,17 @@ def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
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}
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def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
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(ins VReg_32:$src0, VReg_32:$src1, SReg_64:$src2,
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(ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
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InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
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"V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
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[(set (i32 VReg_32:$dst), (select (i1 SReg_64:$src2),
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VReg_32:$src1, VReg_32:$src0))]
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[(set (i32 VReg_32:$dst), (select (i1 SSrc_64:$src2),
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VSrc_32:$src1, VSrc_32:$src0))]
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>;
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//f32 pattern for V_CNDMASK_B32_e64
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def : Pat <
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(f32 (select (i1 SReg_64:$src2), VReg_32:$src1, VReg_32:$src0)),
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(V_CNDMASK_B32_e64 VReg_32:$src0, VReg_32:$src1, SReg_64:$src2)
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(f32 (select (i1 SSrc_64:$src2), VSrc_32:$src1, VSrc_32:$src0)),
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(V_CNDMASK_B32_e64 VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2)
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>;
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defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>;
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@ -895,7 +895,7 @@ def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
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def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
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def : Pat <
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(mul VSrc_32:$src0, VReg_32:$src1),
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(V_MUL_LO_I32 VSrc_32:$src0, VReg_32:$src1, (i32 SIOperand.ZERO), 0, 0, 0, 0)
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(V_MUL_LO_I32 VSrc_32:$src0, VReg_32:$src1, (i32 0), 0, 0, 0, 0)
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>;
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def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
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def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
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@ -1219,19 +1219,19 @@ def : BitConvert <f32, i32, VReg_32>;
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def : Pat <
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(int_AMDIL_clamp VReg_32:$src, (f32 FP_ZERO), (f32 FP_ONE)),
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(V_ADD_F32_e64 VReg_32:$src, (i32 0x80 /* SRC1 */),
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(V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */),
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0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
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>;
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def : Pat <
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(fabs VReg_32:$src),
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(V_ADD_F32_e64 VReg_32:$src, (i32 0x80 /* SRC1 */),
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(V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */),
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1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */)
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>;
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def : Pat <
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(fneg VReg_32:$src),
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(V_ADD_F32_e64 VReg_32:$src, (i32 0x80 /* SRC1 */),
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(V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */),
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0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */)
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>;
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@ -1394,8 +1394,8 @@ def : Pat <
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/********** VOP3 Patterns **********/
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/********** ================== **********/
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def : Pat <(f32 (fadd (fmul VSrc_32:$src0, VReg_32:$src1), VReg_32:$src2)),
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(V_MAD_F32 VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2,
|
||||
def : Pat <(f32 (fadd (fmul VSrc_32:$src0, VSrc_32:$src1), VSrc_32:$src2)),
|
||||
(V_MAD_F32 VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
|
||||
0, 0, 0, 0)>;
|
||||
|
||||
/********** ================== **********/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user