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mi-sched: Force bottom up scheduling for generic targets.

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Fast register pressure tracking currently only takes effect during
bottom up scheduling. Forcing this is a bit faster and simpler for
targets that don't have many scheduling constraints and don't need
top-down scheduling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190014 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-09-04 23:54:00 +00:00
parent a38c27be0f
commit d4486ebd5f
3 changed files with 34 additions and 19 deletions
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26
lib/CodeGen/MachineScheduler.cpp
View File

@ -1594,6 +1594,12 @@ private:
SchedBoundary Top;
SchedBoundary Bot;
// Allow the driver to force top-down or bottom-up scheduling. If neither is
// true, the scheduler runs in both directions and converges. For generic
// targets, we default to bottom-up, because it's simpler and more
// compile-time optimizations have been implemented in that direction.
bool OnlyBottomUp;
bool OnlyTopDown;
public:
/// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
enum {
@ -1604,7 +1610,8 @@ public:
ConvergingScheduler(const MachineSchedContext *C):
Context(C), DAG(0), SchedModel(0), TRI(0),
Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
Top(TopQID, "TopQ"), Bot(BotQID, "BotQ"),
OnlyBottomUp(true), OnlyTopDown(false) {}
virtual bool shouldTrackPressure(unsigned NumRegionInstrs);
@ -1709,6 +1716,19 @@ void ConvergingScheduler::initialize(ScheduleDAGMI *dag) {
}
assert((!ForceTopDown || !ForceBottomUp) &&
"-misched-topdown incompatible with -misched-bottomup");
// Check -misched-topdown/bottomup can force or unforce scheduling direction.
// e.g. -misched-bottomup=false allows scheduling in both directions.
if (ForceBottomUp.getNumOccurrences() > 0) {
OnlyBottomUp = ForceBottomUp;
if (OnlyBottomUp)
OnlyTopDown = false;
}
if (ForceTopDown.getNumOccurrences() > 0) {
OnlyTopDown = ForceTopDown;
if (OnlyTopDown)
OnlyBottomUp = false;
}
}
void ConvergingScheduler::releaseTopNode(SUnit *SU) {
@ -2674,7 +2694,7 @@ SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
}
SUnit *SU;
do {
if (ForceTopDown) {
if (OnlyTopDown) {
SU = Top.pickOnlyChoice();
if (!SU) {
CandPolicy NoPolicy;
@ -2686,7 +2706,7 @@ SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
}
IsTopNode = true;
}
else if (ForceBottomUp) {
else if (OnlyBottomUp) {
SU = Bot.pickOnlyChoice();
if (!SU) {
CandPolicy NoPolicy;

18
test/CodeGen/X86/misched-copy.ll
View File

@ -1,12 +1,4 @@
; REQUIRES: asserts
;
; FIXME: The following line is a hack to remove any stray files which might have
; been left dangling around by this test. It can be removed once the various
; bots have cycled past this commit.
;
; RUN: rm -f misched-copy.s %S/misched-copy.s
;
;
; RUN: llc < %s -march=x86 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
;
; Test scheduling of copy instructions.
@ -16,11 +8,11 @@
; MUL_HiLo PhysReg use copies should be just above the mul.
; MUL_HiLo PhysReg def copies should be just below the mul.
;
; CHECK: *** Final schedule for BB#1 ***
; CHECK-NEXT: %EAX<def> = COPY
; CHECK: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>;
; CHECK-NEXT: COPY %E{{[AD]}}X;
; CHECK-NEXT: COPY %E{{[AD]}}X;
; CHECK: *** Final schedule for BB#1 ***
; CHECK: %EAX<def> = COPY
; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>;
; CHECK-NEXT: COPY %E{{[AD]}}X
; CHECK-NEXT: COPY %E{{[AD]}}X
; CHECK: DIVSSrm
define i64 @mulhoist(i32 %a, i32 %b) #0 {
entry:

9
test/CodeGen/X86/misched-matmul.ll
View File

@ -3,11 +3,14 @@
;
; Verify that register pressure heuristics are working in MachineScheduler.
;
; When we enable subtree scheduling heuristics on X86, we may need a
; flag to disable it for this test case.
; We can further reduce spills in this case with a global register
; pressure heuristic, like sethi-ullman numbers or biasing toward
; scheduled subtrees. However, these heuristics are marginally
; beneficial on x86_64 and exacerbate register pressure in other
; more complex cases.
;
; CHECK: @wrap_mul4
; CHECK: 22 regalloc - Number of spills inserted
; CHECK: 23 regalloc - Number of spills inserted
define void @wrap_mul4(double* nocapture %Out, [4 x double]* nocapture %A, [4 x double]* nocapture %B) #0 {
entry: