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No functionality change. Fix up some whitespace and switch out "" for '' when

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printing a single character.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128256 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nick Lewycky 2011-03-25 06:04:26 +00:00
parent eb5067e0d9
commit d56acb36ab
1 changed files with 3 additions and 3 deletions
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6
lib/CodeGen/RegAllocLinearScan.cpp
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@ -375,7 +375,7 @@ namespace {
dbgs() << str << " intervals:\n";
for (; i != e; ++i) {
dbgs() << "\t" << *i->first << " -> ";
dbgs() << '\t' << *i->first << " -> ";
unsigned reg = i->first->reg;
if (TargetRegisterInfo::isVirtualRegister(reg))
@ -390,7 +390,7 @@ namespace {
}
INITIALIZE_PASS_BEGIN(RALinScan, "linearscan-regalloc",
"Linear Scan Register Allocator", false, false)
"Linear Scan Register Allocator", false, false)
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
INITIALIZE_PASS_DEPENDENCY(CalculateSpillWeights)
@ -401,7 +401,7 @@ INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
INITIALIZE_AG_DEPENDENCY(RegisterCoalescer)
INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
INITIALIZE_PASS_END(RALinScan, "linearscan-regalloc",
"Linear Scan Register Allocator", false, false)
"Linear Scan Register Allocator", false, false)
void RALinScan::ComputeRelatedRegClasses() {
// First pass, add all reg classes to the union, and determine at least one