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Optimize GEP off of intermediate allocas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116681 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -33,7 +33,9 @@
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/CallSite.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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@ -658,21 +660,13 @@ bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, AddrBase &Base,
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break;
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}
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case Instruction::Alloca: {
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// TODO: Fix this to do intermediate loads, etc.
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if (Offset != 0) return false;
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const AllocaInst *AI = cast<AllocaInst>(Obj);
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DenseMap<const AllocaInst*, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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Base.Reg = ARM::SP;
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Base.FrameIndex = SI->second;
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return true;
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}
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// Don't handle dynamic allocas.
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assert(!FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Obj)) &&
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"Alloca should have been handled earlier!");
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return false;
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unsigned Reg = TargetMaterializeAlloca(AI);
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if (Reg == 0) return false;
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Base.Reg = Reg;
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return true;
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}
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}
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@ -766,6 +760,24 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
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ResultReg, Base.FrameIndex, RC,
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TM.getRegisterInfo());
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else if (Base.Reg == ARM::SP) {
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// TODO: This won't work for NEON.
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unsigned FI = Base.FrameIndex;
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MachineMemOperand *MMO =
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FuncInfo.MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(FI, Offset),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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if (isFloat || isThumb)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addFrameIndex(FI).addReg(0).addImm(Offset).addMemOperand(MMO));
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}
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// The thumb and floating point instructions both take 2 operands, ARM takes
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// another register.
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else if (isFloat || isThumb)
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@ -838,6 +850,26 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
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TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
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SrcReg, true /*isKill*/, Base.FrameIndex,
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TLI.getRegClassFor(VT), TM.getRegisterInfo());
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else if (Base.Reg == ARM::SP) {
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// TODO: This won't work for NEON.
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unsigned FI = Base.FrameIndex;
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MachineMemOperand *MMO =
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FuncInfo.MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(FI, Offset),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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if (isFloat || isThumb)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg, getKillRegState(true))
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.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO));
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else
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg, getKillRegState(true))
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.addFrameIndex(FI).addReg(0).addImm(Offset).addMemOperand(MMO));
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}
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// The thumb addressing mode has operands swapped from the arm addressing
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// mode, the floating point one only has two operands.
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else if (isFloat || isThumb)
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