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Weekly fix of register allocation dependent unit tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130567 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-04-30 01:37:52 +00:00
parent d65ba721cc
commit d5b679c8ce
7 changed files with 40 additions and 33 deletions
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4
test/CodeGen/ARM/arm-and-tst-peephole.ll
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@ -23,7 +23,7 @@ tailrecurse: ; preds = %sw.bb, %entry
%tmp2 = load i8** %scevgep5
%0 = ptrtoint i8* %tmp2 to i32
; ARM: ands r12, r12, #3
; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3
; ARM-NEXT: beq
; THUMB: movs r[[R0:[0-9]+]], #3
@ -31,7 +31,7 @@ tailrecurse: ; preds = %sw.bb, %entry
; THUMB-NEXT: cmp r[[R0]], #0
; THUMB-NEXT: beq
; T2: ands r12, r12, #3
; T2: ands {{r[0-9]+}}, {{r[0-9]+}}, #3
; T2-NEXT: beq
%and = and i32 %0, 3

19
test/CodeGen/ARM/indirectbr.ll
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@ -42,20 +42,23 @@ L3: ; preds = %L4, %bb2
br label %L2
L2: ; preds = %L3, %bb2
; THUMB: muls
%res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i32> [#uses=1]
%phitmp = mul i32 %res.2, 6 ; <i32> [#uses=1]
br label %L1
L1: ; preds = %L2, %bb2
%res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
; ARM: ldr r1, LCPI
; ARM: add r1, pc, r1
; ARM: str r1
; THUMB: ldr.n r2, LCPI
; THUMB: add r2, pc
; THUMB: str r2
; THUMB2: ldr.n r2, LCPI
; THUMB2-NEXT: str r2
; ARM: ldr [[R1:r[0-9]+]], LCPI
; ARM: add [[R1b:r[0-9]+]], pc, [[R1]]
; ARM: str [[R1b]]
; THUMB: ldr.n
; THUMB: add
; THUMB: ldr.n [[R2:r[0-9]+]], LCPI
; THUMB: add [[R2]], pc
; THUMB: str [[R2]]
; THUMB2: ldr.n [[R2:r[0-9]+]], LCPI
; THUMB2-NEXT: str{{(.w)?}} [[R2]]
store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
ret i32 %res.3
}

4
test/CodeGen/ARM/ldrd.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V6
; RUN: llc < %s -mtriple=armv5-apple-darwin | FileCheck %s -check-prefix=V5
; RUN: llc < %s -mtriple=armv6-eabi | FileCheck %s -check-prefix=EABI
; RUN: llc < %s -mtriple=armv5-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V5
; RUN: llc < %s -mtriple=armv6-eabi -regalloc=linearscan | FileCheck %s -check-prefix=EABI
; rdar://r6949835
; Magic ARM pair hints works best with linearscan.

8
test/CodeGen/ARM/lsr-code-insertion.ll
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@ -1,5 +1,4 @@
; RUN: llc < %s -stats |& grep {39.*Number of machine instrs printed}
; RUN: llc < %s -stats |& not grep {.*Number of re-materialization}
; RUN: llc < %s | FileCheck %s
; This test really wants to check that the resultant "cond_true" block only
; has a single store in it, and that cond_true55 only has code to materialize
; the constant and do a store. We do *not* want something like this:
@ -8,6 +7,11 @@
; add r8, r0, r6
; str r10, [r8, #+4]
;
; CHECK: ldr [[R6:r[0-9*]+]], LCP
; CHECK: cmp {{.*}}, [[R6]]
; CHECK: ldrle
; CHECK-NEXT: strle
target triple = "arm-apple-darwin8"
define void @foo(i32* %mc, i32* %mpp, i32* %ip, i32* %dpp, i32* %tpmm, i32 %M, i32* %tpim, i32* %tpdm, i32* %bp, i32* %ms, i32 %xmb) {

16
test/CodeGen/ARM/unaligned_load_store.ll
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@ -8,14 +8,14 @@
define void @t(i8* nocapture %a, i8* nocapture %b) nounwind {
entry:
; GENERIC: t:
; GENERIC: ldrb r2
; GENERIC: ldrb r3
; GENERIC: ldrb r12
; GENERIC: ldrb r1
; GENERIC: strb r1
; GENERIC: strb r12
; GENERIC: strb r3
; GENERIC: strb r2
; GENERIC: ldrb [[R2:r[0-9]+]]
; GENERIC: ldrb [[R3:r[0-9]+]]
; GENERIC: ldrb [[R12:r[0-9]+]]
; GENERIC: ldrb [[R1:r[0-9]+]]
; GENERIC: strb [[R1]]
; GENERIC: strb [[R12]]
; GENERIC: strb [[R3]]
; GENERIC: strb [[R2]]
; DARWIN_V6: t:
; DARWIN_V6: ldr r1

20
test/CodeGen/Thumb2/machine-licm.ll
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@ -14,19 +14,19 @@ entry:
bb.nph: ; preds = %entry
; CHECK: BB#1
; CHECK: movw r2, :lower16:L_GV$non_lazy_ptr
; CHECK: movt r2, :upper16:L_GV$non_lazy_ptr
; CHECK: ldr r2, [r2]
; CHECK: ldr r3, [r2]
; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr
; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr
; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
; CHECK: ldr{{.*}}, [r[[R2b]]
; CHECK: LBB0_2
; CHECK-NOT: LCPI0_0:
; PIC: BB#1
; PIC: movw r2, :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4))
; PIC: movt r2, :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4))
; PIC: add r2, pc
; PIC: ldr r2, [r2]
; PIC: ldr r3, [r2]
; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4))
; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4))
; PIC: add r[[R2]], pc
; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
; PIC: ldr{{.*}}, [r[[R2b]]
; PIC: LBB0_2
; PIC-NOT: LCPI0_0:
; PIC: .section
@ -89,7 +89,7 @@ bb.nph:
; CHECK: bb.nph
; CHECK: movw {{(r[0-9])|(lr)}}, #32768
; CHECK: movs {{(r[0-9]+)|(lr)}}, #0
; CHECK: movw [[REGISTER:(r[0-9])|(lr)]], #16386
; CHECK: movw [[REGISTER:(r[0-9]+)|(lr)]], #16386
; CHECK: movw {{(r[0-9]+)|(lr)}}, #65534
; CHECK: movt {{(r[0-9]+)|(lr)}}, #65535
br label %bb

2
test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
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@ -18,7 +18,7 @@ entry:
ret i32 0
}
; CHECK: movq ___stack_chk_guard@GOTPCREL(%rip), %rax
; CHECK: movq ___stack_chk_guard@GOTPCREL(%rip)
; CHECK: movb 38(%rsp), [[R0:%.+]]
; CHECK: movb 8(%rsp), [[R1:%.+]]
; CHECK: movb [[R1]], 8(%rsp)