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Adds an option to disable ARM ld/st optim pass
Enabled by default, but it's useful when debugging with llc. Patch by Ranjeet Singh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233303 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -37,6 +37,11 @@ EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
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" to make use of cmpxchg flow-based information"),
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cl::init(true));
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static cl::opt<bool>
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EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
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cl::desc("Enable ARM load/store optimization pass"),
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cl::init(true));
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extern "C" void LLVMInitializeARMTarget() {
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// Register the target.
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RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
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@ -348,18 +353,22 @@ bool ARMPassConfig::addInstSelector() {
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}
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void ARMPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None)
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addPass(createARMLoadStoreOptimizationPass(true));
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if (getOptLevel() != CodeGenOpt::None)
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(createMLxExpansionPass());
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if (getOptLevel() != CodeGenOpt::None && !DisableA15SDOptimization) {
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addPass(createA15SDOptimizerPass());
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if (EnableARMLoadStoreOpt)
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addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
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if (!DisableA15SDOptimization)
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addPass(createA15SDOptimizerPass());
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}
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}
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void ARMPassConfig::addPreSched2() {
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(createARMLoadStoreOptimizationPass());
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if (EnableARMLoadStoreOpt)
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addPass(createARMLoadStoreOptimizationPass());
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addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
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}
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@ -373,7 +382,7 @@ void ARMPassConfig::addPreSched2() {
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addPass(createThumb2SizeReductionPass());
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if (!getARMSubtarget().isThumb1Only())
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addPass(&IfConverterID);
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}
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}
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addPass(createThumb2ITBlockPass());
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}
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