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https://github.com/c64scene-ar/llvm-6502.git
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[mips] Optimize code generation for 64-bit variable shift instructions.
Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235376 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vasileios Kalintiris
parent
a1fa0de258
commit
d72ba1af57
@ -502,6 +502,16 @@ def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
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def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
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(EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
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// variable shift instructions patterns
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def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
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(DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
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def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
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(DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
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def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
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(DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
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def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
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(DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
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// 32-to-64-bit extension
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def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
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def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
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@ -131,9 +131,7 @@ entry:
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; 32R6: jr $ra
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; 32R6: or $3, $[[T0]], $[[T11]]
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; FIXME: The sll instruction below is redundant.
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; GP64: sll $[[T0:[0-9]+]], $5, 0
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; GP64: dsrav $2, $4, $[[T0]]
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; GP64: dsrav $2, $4, $5
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%r = ashr i64 %a, %b
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ret i64 %r
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@ -146,11 +144,11 @@ entry:
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; GP32: lw $25, %call16(__ashrti3)($gp)
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; M3: sll $[[T0:[0-9]+]], $7, 0
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; M3: dsrav $[[T1:[0-9]+]], $4, $[[T0]]
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; M3: dsrav $[[T1:[0-9]+]], $4, $7
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; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
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; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
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; M3: move $3, $[[T1]]
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; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]]
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; M3: dsrlv $[[T4:[0-9]+]], $5, $7
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; M3: dsll $[[T5:[0-9]+]], $4, 1
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; M3: not $[[T6:[0-9]+]], $[[T0]]
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; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
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@ -163,35 +161,34 @@ entry:
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; M3: jr $ra
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; M3: nop
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; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0
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; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
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; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1
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; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]]
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; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; GP64-NOT-R6: or $3, $[[T4]], $[[T1]]
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; GP64-NOT-R6: dsrav $2, $4, $[[T0]]
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; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32
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; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
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; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
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; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
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; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
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; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
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; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
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; GP64-NOT-R6: dsrav $2, $4, $7
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; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
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; GP64-NOT-R6: movn $3, $2, $[[T5]]
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; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31
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; GP64-NOT-R6: jr $ra
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; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]]
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; 64R6: sll $[[T0:[0-9]+]], $7, 0
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; 64R6: dsrav $[[T1:[0-9]+]], $4, $[[T0]]
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; 64R6: andi $[[T2:[0-9]+]], $[[T0]], 32
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; 64R6: dsrav $[[T0:[0-9]+]], $4, $7
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; 64R6: sll $[[T1:[0-9]+]], $7, 0
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; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 32
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; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0
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; 64R6: seleqz $[[T4:[0-9]+]], $[[T1]], $[[T3]]
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; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]]
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; 64R6: dsra $[[T5:[0-9]+]], $4, 31
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; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]]
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; 64R6: or $2, $[[T6]], $[[T4]]
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; 64R6: dsrlv $[[T7:[0-9]+]], $5, $[[T0]]
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; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7
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; 64R6: dsll $[[T8:[0-9]+]], $4, 1
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; 64R6: not $[[T9:[0-9]+]], $[[T0]]
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; 64R6: not $[[T9:[0-9]+]], $[[T1]]
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; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]]
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; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]]
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; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]]
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; 64R6: selnez $[[T13:[0-9]+]], $[[T1]], $[[T3]]
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; 64R6: selnez $[[T13:[0-9]+]], $[[T0]], $[[T3]]
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; 64R6: jr $ra
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; 64R6: or $3, $[[T13]], $[[T12]]
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@ -125,8 +125,7 @@ entry:
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; 32R6: jr $ra
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; 32R6: seleqz $2, $[[T7]], $[[T5]]
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; GP64: sll $[[T0:[0-9]+]], $5, 0
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; GP64: dsrlv $2, $4, $[[T0]]
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; GP64: dsrlv $2, $4, $5
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%r = lshr i64 %a, %b
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ret i64 %r
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@ -139,11 +138,11 @@ entry:
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; GP32: lw $25, %call16(__lshrti3)($gp)
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; M3: sll $[[T0:[0-9]+]], $7, 0
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; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]]
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; M3: dsrlv $[[T1:[0-9]+]], $4, $7
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; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
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; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
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; M3: move $3, $[[T1]]
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; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]]
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; M3: dsrlv $[[T4:[0-9]+]], $5, $7
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; M3: dsll $[[T5:[0-9]+]], $4, 1
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; M3: not $[[T6:[0-9]+]], $[[T0]]
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; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
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@ -156,32 +155,32 @@ entry:
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; M3: jr $ra
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; M3: nop
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; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0
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; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
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; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1
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; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]]
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; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; GP64-NOT-R6: or $3, $[[T4]], $[[T1]]
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; GP64-NOT-R6: dsrlv $2, $4, $[[T0]]
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; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32
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; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
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; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
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; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
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; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
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; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
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; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
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; GP64-NOT-R6: dsrlv $2, $4, $7
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; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
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; GP64-NOT-R6: movn $3, $2, $[[T5]]
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; GP64-NOT-R6: jr $ra
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; GP64-NOT-R6: movn $2, $zero, $1
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; 64R6: sll $[[T0:[0-9]+]], $7, 0
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; 64R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
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; 64R6: dsll $[[T2:[0-9]+]], $4, 1
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; 64R6: not $[[T3:[0-9]+]], $[[T0]]
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; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]]
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; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32
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; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7
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; 64R6: dsll $[[T1:[0-9]+]], $4, 1
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; 64R6: sll $[[T2:[0-9]+]], $7, 0
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; 64R6: not $[[T3:[0-9]+]], $[[T2]]
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; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
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; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]]
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; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32
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; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
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; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
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; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]]
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; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7
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; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
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; 64R6: or $3, $[[T10]], $[[T8]]
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; 64R6: jr $ra
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; 64R6: seleqz $2, $[[T0]], $[[T7]]
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; 64R6: seleqz $2, $[[T9]], $[[T7]]
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%r = lshr i128 %a, %b
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ret i128 %r
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@ -137,8 +137,7 @@ entry:
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; 32R6: jr $ra
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; 32R6: seleqz $3, $[[T7]], $[[T5]]
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; GP64: sll $[[T0:[0-9]+]], $5, 0
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; GP64: dsllv $2, $4, $1
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; GP64: dsllv $2, $4, $5
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%r = shl i64 %a, %b
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ret i64 %r
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@ -151,11 +150,11 @@ entry:
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; GP32: lw $25, %call16(__ashlti3)($gp)
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; M3: sll $[[T0:[0-9]+]], $7, 0
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; M3: dsllv $[[T1:[0-9]+]], $5, $[[T0]]
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; M3: dsllv $[[T1:[0-9]+]], $5, $7
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; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
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; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
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; M3: move $2, $[[T1]]
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; M3: dsllv $[[T4:[0-9]+]], $4, $[[T0]]
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; M3: dsllv $[[T4:[0-9]+]], $4, $7
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; M3: dsrl $[[T5:[0-9]+]], $5, 1
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; M3: not $[[T6:[0-9]+]], $[[T0]]
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; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
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@ -168,32 +167,32 @@ entry:
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; M3: jr $ra
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; M3: nop
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; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0
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; GP64-NOT-R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]]
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; GP64-NOT-R6: dsrl $[[T2:[0-9]+]], $5, 1
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; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]]
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; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; GP64-NOT-R6: or $2, $[[T1]], $[[T4]]
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; GP64-NOT-R6: dsllv $3, $5, $[[T0]]
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; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32
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; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7
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; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1
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; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
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; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
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; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
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; GP64-NOT-R6: or $2, $[[T0]], $[[T4]]
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; GP64-NOT-R6: dsllv $3, $5, $7
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; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
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; GP64-NOT-R6: movn $2, $3, $[[T5]]
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; GP64-NOT-R6: jr $ra
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; GP64-NOT-R6: movn $3, $zero, $1
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; 64R6: sll $[[T0:[0-9]+]], $7, 0
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; 64R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]]
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; 64R6: dsrl $[[T2:[0-9]+]], $5, 1
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; 64R6: not $[[T3:[0-9]+]], $[[T0]]
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; 64R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; 64R6: or $[[T5:[0-9]+]], $[[T1]], $[[T4]]
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; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32
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; 64R6: dsllv $[[T0:[0-9]+]], $4, $7
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; 64R6: dsrl $[[T1:[0-9]+]], $5, 1
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; 64R6: sll $[[T2:[0-9]+]], $7, 0
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; 64R6: not $[[T3:[0-9]+]], $[[T2]]
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; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
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; 64R6: or $[[T5:[0-9]+]], $[[T0]], $[[T4]]
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; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32
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; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
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; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
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; 64R6: dsllv $[[T9:[0-9]+]], $5, $[[T0]]
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; 64R6: dsllv $[[T9:[0-9]+]], $5, $7
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; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
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; 64R6: or $2, $[[T10]], $[[T8]]
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; 64R6: jr $ra
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; 64R6: seleqz $3, $[[T0]], $[[T7]]
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; 64R6: seleqz $3, $[[T9]], $[[T7]]
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%r = shl i128 %a, %b
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ret i128 %r
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@ -65,7 +65,8 @@ entry:
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define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: drotrv
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; CHECK-NOT: sll
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; CHECK: drotrv
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%shr = lshr i64 %a0, %a1
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%sub = sub i64 64, %a1
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%shl = shl i64 %a0, %sub
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@ -75,7 +76,8 @@ entry:
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define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: drotrv
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; CHECK-NOT: sll
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; CHECK: drotrv
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%shl = shl i64 %a0, %a1
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%sub = sub i64 64, %a1
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%shr = lshr i64 %a0, %sub
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