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Support returning non-power-of-2 vectors to unblock some work

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44371 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2007-11-27 19:28:48 +00:00
parent 19914ed97f
commit d73ab8884f
2 changed files with 13 additions and 4 deletions
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7
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -364,6 +364,13 @@ unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
unsigned NumVectorRegs = 1; unsigned NumVectorRegs = 1;
// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
// could break down into LHS/RHS like LegalizeDAG does.
if (!isPowerOf2_32(NumElts)) {
NumVectorRegs = NumElts;
NumElts = 1;
}
// Divide the input until we get to a supported size. This will always // Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors. // end with a scalar if the target doesn't support vectors.
while (NumElts > 1 && while (NumElts > 1 &&

10
lib/Target/X86/X86CallingConv.td
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@ -52,10 +52,12 @@ def RetCC_X86_32_C : CallingConv<[
// X86-32 FastCC return-value convention. // X86-32 FastCC return-value convention.
def RetCC_X86_32_Fast : CallingConv<[ def RetCC_X86_32_Fast : CallingConv<[
// The X86-32 fastcc returns FP values in XMM0 if the target has SSE2, // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
// otherwise it is the the C calling conventions. // SSE2, otherwise it is the the C calling conventions.
CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, // This can happen when a float, 2 x float, or 3 x float vector is split by
CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, // target lowering, and is returned in 1-3 sse regs.
CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
CCDelegateTo<RetCC_X86Common> CCDelegateTo<RetCC_X86Common>
]>; ]>;