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R600: Expand vector FNEG

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186913 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-07-23 01:47:46 +00:00
parent 5e4fa97a1d
commit d7a472c9c6
2 changed files with 29 additions and 0 deletions
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3
lib/Target/R600/AMDGPUISelLowering.cpp
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@ -78,6 +78,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::LOAD, MVT::f64, Promote); setOperationAction(ISD::LOAD, MVT::f64, Promote);
AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64); AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
setOperationAction(ISD::MUL, MVT::i64, Expand); setOperationAction(ISD::MUL, MVT::i64, Expand);
setOperationAction(ISD::UDIV, MVT::i32, Expand); setOperationAction(ISD::UDIV, MVT::i32, Expand);

26
test/CodeGen/R600/fneg.ll Normal file
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@ -0,0 +1,26 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; XXX: There is a bug in the DAGCombiner that lowers fneg to XOR, this test
; will need to be changed once it is fixed.
; CHECK: @fneg_v2
; CHECK: XOR_INT
; CHECK: XOR_INT
define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
entry:
%0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
store <2 x float> %0, <2 x float> addrspace(1)* %out
ret void
}
; CHECK: @fneg_v4
; CHECK: XOR_INT
; CHECK: XOR_INT
; CHECK: XOR_INT
; CHECK: XOR_INT
define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
entry:
%0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
store <4 x float> %0, <4 x float> addrspace(1)* %out
ret void
}