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use the MachineInstrBuilder operator-> to simplify some code.
There are probably more instances of this floating around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130474 91177308-0d34-0410-b5e6-96231b3b80d8
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07e7998f09
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@ -1021,7 +1021,7 @@ reMaterialize(MachineBasicBlock &MBB,
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MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
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DestReg)
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.addConstantPoolIndex(CPI).addImm(PCLabelId);
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(*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
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MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
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break;
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}
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}
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@ -457,7 +457,7 @@ void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
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TransferImpOps(MI, MIB, MIB);
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// Transfer memoperands.
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(*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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MI.eraseFromParent();
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}
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@ -500,13 +500,12 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
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MIB.addOperand(MI.getOperand(OpIdx++));
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MIB.addOperand(MI.getOperand(OpIdx++));
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if (SrcIsKill)
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// Add an implicit kill for the super-reg.
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(*MIB).addRegisterKilled(SrcReg, TRI, true);
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if (SrcIsKill) // Add an implicit kill for the super-reg.
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MIB->addRegisterKilled(SrcReg, TRI, true);
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TransferImpOps(MI, MIB, MIB);
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// Transfer memoperands.
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(*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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MI.eraseFromParent();
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}
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@ -630,9 +629,8 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
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MIB.addOperand(MI.getOperand(OpIdx++));
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MIB.addOperand(MI.getOperand(OpIdx++));
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if (SrcIsKill)
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// Add an implicit kill for the super-reg.
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(*MIB).addRegisterKilled(SrcReg, TRI, true);
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if (SrcIsKill) // Add an implicit kill for the super-reg.
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MIB->addRegisterKilled(SrcReg, TRI, true);
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TransferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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}
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@ -663,8 +661,8 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
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unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
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LO16 = LO16.addImm(SOImmValV1);
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HI16 = HI16.addImm(SOImmValV2);
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(*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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(*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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LO16.addImm(Pred).addReg(PredReg).addReg(0);
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HI16.addImm(Pred).addReg(PredReg).addReg(0);
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TransferImpOps(MI, LO16, HI16);
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@ -700,8 +698,8 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
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HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
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}
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(*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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(*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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LO16.addImm(Pred).addReg(PredReg);
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HI16.addImm(Pred).addReg(PredReg);
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@ -864,7 +862,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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TII->get(ARM::BL))
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.addExternalSymbol("__aeabi_read_tp", 0);
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(*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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TransferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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return true;
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@ -879,7 +877,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(NewLdOpc), DstReg)
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.addOperand(MI.getOperand(1)));
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(*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(ARM::tPICADD))
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
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@ -935,7 +933,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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if (isARM) {
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AddDefaultPred(MIB3);
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if (Opcode == ARM::MOV_ga_pcrel_ldr)
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(*MIB2).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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MIB2->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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}
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TransferImpOps(MI, MIB1, MIB3);
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MI.eraseFromParent();
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@ -1027,9 +1025,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
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MIB.addReg(D0).addReg(D1);
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if (SrcIsKill)
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// Add an implicit kill for the Q register.
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(*MIB).addRegisterKilled(SrcReg, TRI, true);
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if (SrcIsKill) // Add an implicit kill for the Q register.
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MIB->addRegisterKilled(SrcReg, TRI, true);
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TransferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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@ -761,7 +761,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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MIB.addOperand(MI->getOperand(OpNum));
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// Transfer memoperands.
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(*MIB).setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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MBB.erase(MBBI);
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return true;
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@ -465,7 +465,7 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
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MIB.addOperand(MI->getOperand(OpNum));
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// Transfer memoperands.
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(*MIB).setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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// Transfer MI flags.
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MIB.setMIFlags(MI->getFlags());
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