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Enable predication of NEON instructions in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89748 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -39,10 +39,6 @@ static cl::opt<bool>
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EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
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cl::desc("Enable ARM 2-addr to 3-addr conv"));
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static cl::opt<bool>
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PredicateNEON("predicate-neon", cl::Hidden,
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cl::desc("Allow NEON instructions to be predicated"));
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ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
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: TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
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Subtarget(STI) {
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@ -417,7 +413,7 @@ bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
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if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
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ARMFunctionInfo *AFI =
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MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
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return PredicateNEON && AFI->isThumb2Function();
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return AFI->isThumb2Function();
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}
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return true;
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}
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29
test/CodeGen/Thumb2/ifcvt-neon.ll
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29
test/CodeGen/Thumb2/ifcvt-neon.ll
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@ -0,0 +1,29 @@
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; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s
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; rdar://7368193
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@a = common global float 0.000000e+00 ; <float*> [#uses=2]
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@b = common global float 0.000000e+00 ; <float*> [#uses=1]
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define arm_apcscc float @t(i32 %c) nounwind {
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entry:
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%0 = icmp sgt i32 %c, 1 ; <i1> [#uses=1]
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%1 = load float* @a, align 4 ; <float> [#uses=2]
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%2 = load float* @b, align 4 ; <float> [#uses=2]
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br i1 %0, label %bb, label %bb1
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bb: ; preds = %entry
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; CHECK: ite lt
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; CHECK: vsublt.f32
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; CHECK-NEXT: vaddge.f32
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%3 = fadd float %1, %2 ; <float> [#uses=1]
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br label %bb2
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bb1: ; preds = %entry
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%4 = fsub float %1, %2 ; <float> [#uses=1]
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br label %bb2
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bb2: ; preds = %bb1, %bb
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%storemerge = phi float [ %4, %bb1 ], [ %3, %bb ] ; <float> [#uses=2]
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store float %storemerge, float* @a
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ret float %storemerge
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}
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