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Increase the number of bits used internally by the ARM target to represent the

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addressing mode from four to five.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115645 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-05 18:14:55 +00:00
parent 737cd213e3
commit d86609fca4
2 changed files with 16 additions and 16 deletions
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14
lib/Target/ARM/ARMBaseInstrInfo.h
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@ -33,7 +33,7 @@ namespace ARMII {
//===------------------------------------------------------------------===//
// This four-bit field describes the addressing mode used.
AddrModeMask = 0xf,
AddrModeMask = 0x1f,
AddrModeNone = 0,
AddrMode1 = 1,
AddrMode2 = 2,
@ -52,7 +52,7 @@ namespace ARMII {
AddrModeT2_i8s4 = 15, // i8 * 4
// Size* - Flags to keep track of the size of an instruction.
SizeShift = 4,
SizeShift = 5,
SizeMask = 7 << SizeShift,
SizeSpecial = 1, // 0 byte pseudo or special case.
Size8Bytes = 2,
@ -61,7 +61,7 @@ namespace ARMII {
// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
// and store ops only. Generic "updating" flag is used for ld/st multiple.
IndexModeShift = 7,
IndexModeShift = 8,
IndexModeMask = 3 << IndexModeShift,
IndexModePre = 1,
IndexModePost = 2,
@ -70,7 +70,7 @@ namespace ARMII {
//===------------------------------------------------------------------===//
// Instruction encoding formats.
//
FormShift = 9,
FormShift = 10,
FormMask = 0x3f << FormShift,
// Pseudo instructions
@ -143,15 +143,15 @@ namespace ARMII {
// UnaryDP - Indicates this is a unary data processing instruction, i.e.
// it doesn't have a Rn operand.
UnaryDP = 1 << 15,
UnaryDP = 1 << 16,
// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
// a 16-bit Thumb instruction if certain conditions are met.
Xform16Bit = 1 << 16,
Xform16Bit = 1 << 17,
//===------------------------------------------------------------------===//
// Code domain.
DomainShift = 17,
DomainShift = 18,
DomainMask = 3 << DomainShift,
DomainGeneral = 0 << DomainShift,
DomainVFP = 1 << DomainShift,

18
lib/Target/ARM/ARMInstrFormats.td
View File

@ -85,8 +85,8 @@ class Xform16Bit { bit canXformTo16Bit = 1; }
//
// Addressing mode.
class AddrMode<bits<4> val> {
bits<4> Value = val;
class AddrMode<bits<5> val> {
bits<5> Value = val;
}
def AddrModeNone : AddrMode<0>;
def AddrMode1 : AddrMode<1>;
@ -199,13 +199,13 @@ class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
bit canXformTo16Bit = 0;
// The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
let TSFlags{3-0} = AM.Value;
let TSFlags{6-4} = SZ.Value;
let TSFlags{8-7} = IndexModeBits;
let TSFlags{14-9} = Form;
let TSFlags{15} = isUnaryDataProc;
let TSFlags{16} = canXformTo16Bit;
let TSFlags{18-17} = D.Value;
let TSFlags{4-0} = AM.Value;
let TSFlags{7-5} = SZ.Value;
let TSFlags{9-8} = IndexModeBits;
let TSFlags{15-10} = Form;
let TSFlags{16} = isUnaryDataProc;
let TSFlags{17} = canXformTo16Bit;
let TSFlags{19-18} = D.Value;
let Constraints = cstr;
let Itinerary = itin;