mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-17 06:33:21 +00:00
Expand bitcast support in fast isel to support bitcasts of non-constant values by emitting reg-reg copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55340 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
ab6c3bb44d
commit
d894f1d274
@ -234,8 +234,36 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
|
||||
} else
|
||||
// TODO: Support vector and fp constants.
|
||||
return I;
|
||||
} else if (!isa<Constant>(I->getOperand(0))) {
|
||||
// Bitcasts of non-constant values become reg-reg copies.
|
||||
MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
|
||||
MVT DstVT = MVT::getMVT(I->getOperand(0)->getType());
|
||||
|
||||
if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
|
||||
DstVT == MVT::Other || !DstVT.isSimple() ||
|
||||
!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
|
||||
// Unhandled type. Halt "fast" selection and bail.
|
||||
return I;
|
||||
if (!TLI.isConvertLegal(SrcVT, DstVT))
|
||||
// Illegal conversion. Halt "fast" selection and bail.
|
||||
return I:
|
||||
|
||||
// Otherwise, insert a register-to-register copy.
|
||||
TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
|
||||
TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
|
||||
unsigned Op0 = ValueMap[I->getOperand(0)];
|
||||
unsigned ResultReg = createResultReg(DstClass);
|
||||
|
||||
if (Op0 == 0)
|
||||
// Unhandled operand. Halt "fast" selection and bail.
|
||||
return false;
|
||||
|
||||
TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Op0, DstClass, SrcClass);
|
||||
ValueMap[I] = ResultReg;
|
||||
|
||||
break;
|
||||
} else
|
||||
// TODO: Support non-constant bitcasts.
|
||||
// Casting a non-integral constant?
|
||||
return I;
|
||||
|
||||
default:
|
||||
|
Loading…
x
Reference in New Issue
Block a user