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some hoovering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25643 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2,8 +2,8 @@
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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// This file was developed by Duraid Madina and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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@ -56,7 +56,8 @@ namespace {
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std::set<unsigned> PendingRegWrites; // XXX: ugly global, but
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// pending writes can cross basic blocks. Note that
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// taken branches end instruction groups.
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// taken branches end instruction groups. So we
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// only need to worry about 'fallthrough' code
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};
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} // end of anonymous namespace
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@ -501,10 +501,13 @@ def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
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def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
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"shr $dst = $src1, $imm">;
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def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
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def EXTRU : AForm<0x03, 0x0b,
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(ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
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"extr.u $dst = $src1, $imm1, $imm2">;
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def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2">;
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def DEPZ : AForm<0x03, 0x0b,
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(ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
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"dep.z $dst = $src1, $imm1, $imm2">;
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def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
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"($qp) cmp.eq.or $dst, p0 = $src1, $src2">;
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@ -168,8 +168,8 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
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if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
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//fix up the old:
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MI.SetMachineOperandReg(i, IA64::r22);
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MachineOperand &MO = MI.getOperand(i);
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MO.setUse(); // mark r22 as being used (the bundler wants to know this)
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MI.getOperand(i).setUse(); // mark r22 as being used
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// (the bundler wants to know this)
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//insert the new
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MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
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.addReg(BaseRegister).addSImm(Offset);
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@ -177,8 +177,8 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
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} else { // it's big
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//fix up the old:
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MI.SetMachineOperandReg(i, IA64::r22);
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MachineOperand &MO = MI.getOperand(i);
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MO.setUse(); // mark r22 as being used (the bundler wants to know this)
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MI.getOperand(i).setUse(); // mark r22 as being used
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// (the bundler wants to know this)
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MachineInstr* nMI;
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nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset);
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MBB.insert(II, nMI);
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