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Fix ARM handling of tBcc branch relaxation.
rdar://10069056 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145885 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -146,11 +146,13 @@ bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCInstFragment *DF,
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const MCAsmLayout &Layout) const {
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// FIXME: This isn't correct for ARM. Just moving the "generic" logic
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// into the targets for now.
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// Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
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// low bit being an implied zero. There's an implied +4 offset for the
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// branch, so we adjust the other way here to determine what's
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// encodable.
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//
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// Relax if the value is too big for a (signed) i8.
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return int64_t(Value) != int64_t(int8_t(Value));
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return int64_t((Value - 4)>>1) != int64_t(int8_t((Value - 4)>>1));
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}
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void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
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14
test/MC/MachO/relax-thumb2-branches.s
Normal file
14
test/MC/MachO/relax-thumb2-branches.s
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@ -0,0 +1,14 @@
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@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s
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ble Lfoo @ wide encoding
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.space 258
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Lfoo:
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nop
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ble Lbaz @ narrow encoding
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.space 256
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Lbaz:
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@ CHECK: '_section_data', '40f38180
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@ CHECK: 000000bf 7fdd
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