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https://github.com/c64scene-ar/llvm-6502.git
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Use i32 for all SPARC shift amounts, even in 64-bit mode.
Test case by llvm-stress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179477 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1415,7 +1415,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
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case CodeModel::Medium: {
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case CodeModel::Medium: {
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// abs44.
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// abs44.
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SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG);
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SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG);
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H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getIntPtrConstant(12));
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H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
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SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG);
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SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG);
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L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
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L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
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return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
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return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
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@@ -1423,7 +1423,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
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case CodeModel::Large: {
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case CodeModel::Large: {
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// abs64.
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// abs64.
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SDValue Hi = makeHiLoPair(Op, SPII::MO_HH, SPII::MO_HM, DAG);
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SDValue Hi = makeHiLoPair(Op, SPII::MO_HH, SPII::MO_HM, DAG);
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Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getIntPtrConstant(32));
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Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
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SDValue Lo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
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SDValue Lo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
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return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
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return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
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}
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}
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@@ -71,6 +71,7 @@ namespace llvm {
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getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
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getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
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virtual SDValue
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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LowerFormalArguments(SDValue Chain,
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@@ -133,7 +133,7 @@ def HM10 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(Val, MVT::i32);
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return CurDAG->getTargetConstant(Val, MVT::i32);
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}]>;
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}]>;
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def : Pat<(i64 imm:$val),
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def : Pat<(i64 imm:$val),
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(ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i64 32)),
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(ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)),
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(ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
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(ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
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Requires<[Is64Bit]>;
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Requires<[Is64Bit]>;
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@@ -142,10 +142,10 @@ class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
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// Define rr and ri shift instructions with patterns.
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// Define rr and ri shift instructions with patterns.
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multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
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multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
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ValueType VT, RegisterClass RC> {
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ValueType VT, RegisterClass RC> {
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def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, RC:$rs2),
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def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
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!strconcat(OpcStr, " $rs, $rs2, $rd"),
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!strconcat(OpcStr, " $rs, $rs2, $rd"),
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[(set VT:$rd, (OpNode VT:$rs, VT:$rs2))]>;
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[(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
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def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, unknown:$shcnt),
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def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
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!strconcat(OpcStr, " $rs, $shcnt, $rd"),
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!strconcat(OpcStr, " $rs, $shcnt, $rd"),
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[(set VT:$rd, (OpNode VT:$rs, (VT imm:$shcnt)))]>;
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[(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
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}
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}
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@@ -144,3 +144,13 @@ define void @stores(i64* %p, i32* %q, i16* %r, i8* %s) {
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ret void
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ret void
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}
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}
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; CHECK: promote_shifts
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; CHECK: ldub [%i0], [[R:%[goli][0-7]]]
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; CHECK: sll [[R]], [[R]], %i0
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define i8 @promote_shifts(i8* %p) {
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%L24 = load i8* %p
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%L32 = load i8* %p
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%B36 = shl i8 %L24, %L32
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ret i8 %B36
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}
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