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[mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186642 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -141,16 +141,6 @@ class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
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[(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
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class MFC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
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[(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
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class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
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[(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
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class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
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@ -341,8 +331,8 @@ defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
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// regardless of register aliasing.
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/// Move Control Registers From/To CPU Registers
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def CFC1 : MFC1_FT_CCR<"cfc1", CPURegsOpnd, CCROpnd, IIFmove>, MFC1_FM<2>;
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def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegsOpnd, IIFmove>, MFC1_FM<6>;
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def CFC1 : MFC1_FT<"cfc1", CPURegsOpnd, CCROpnd, IIFmove>, MFC1_FM<2>;
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def CTC1 : MTC1_FT<"ctc1", CCROpnd, CPURegsOpnd, IIFmove>, MFC1_FM<6>;
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def MFC1 : MFC1_FT<"mfc1", CPURegsOpnd, FGR32RegsOpnd, IIFmoveC1, bitconvert>,
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MFC1_FM<0>;
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def MTC1 : MTC1_FT<"mtc1", FGR32RegsOpnd, CPURegsOpnd, IIFmoveC1, bitconvert>,
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@ -549,7 +539,6 @@ def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
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//===----------------------------------------------------------------------===//
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// Floating Point Pseudo-Instructions
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//===----------------------------------------------------------------------===//
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def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCROpnd:$src), []>;
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// This pseudo instr gets expanded into 2 mtc1 instrs after register
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// allocation.
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@ -141,8 +141,6 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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Opc = Mips::FMOV_D32;
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else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D64;
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else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
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Opc = Mips::MOVCCRToCCR;
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else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
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if (Mips::CPU64RegsRegClass.contains(SrcReg))
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Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
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