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Add bunch of reg-imm movs

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75921 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-07-16 13:34:50 +00:00
parent fc9ceeaad8
commit da308c9a67
3 changed files with 104 additions and 4 deletions
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6
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -56,6 +56,12 @@ namespace {
return CurDAG->getTargetConstant(Imm, MVT::i16);
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
// Include the pieces autogenerated from the target description.
#include "SystemZGenDAGISel.inc"

51
lib/Target/SystemZ/SystemZInstrInfo.td
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@ -45,6 +45,16 @@ def HH16 : SDNodeXForm<imm, [{
return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
}]>;
def LO32 : SDNodeXForm<imm, [{
// Transformation function: return low 32 bits.
return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
}]>;
def HI32 : SDNodeXForm<imm, [{
// Transformation function: return bits 32-63.
return getI32Imm(N->getZExtValue() >> 32);
}]>;
def i64ll16 : PatLeaf<(i64 imm), [{
// i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
// bits set.
@ -73,6 +83,24 @@ def immSExt16 : PatLeaf<(i64 imm), [{
return ((int64_t)val == (int16_t)val);
}]>;
def immSExt32 : PatLeaf<(i64 imm), [{
// immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
// field.
uint64_t val = N->getZExtValue();
return ((int64_t)val == (int32_t)val);
}]>;
def i64lo32 : PatLeaf<(i64 imm), [{
// i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
// bits set.
return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
}], LO32>;
def i64hi32 : PatLeaf<(i64 imm), [{
// i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
}], HI32>;
//===----------------------------------------------------------------------===//
// Control Flow Instructions...
//
@ -97,6 +125,29 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
"lghi\t{$dst, $src}",
[(set GR64:$dst, immSExt16:$src)]>;
def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
"llill\t{$dst, $src}",
[(set GR64:$dst, i64ll16:$src)]>;
def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
"llilh\t{$dst, $src}",
[(set GR64:$dst, i64lh16:$src)]>;
def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
"llihl\t{$dst, $src}",
[(set GR64:$dst, i64hl16:$src)]>;
def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
"llihh\t{$dst, $src}",
[(set GR64:$dst, i64hh16:$src)]>;
// FIXME: these 3 instructions seem to require extimm facility
def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
"lgfi\t{$dst, $src}",
[(set GR64:$dst, immSExt32:$src)]>;
def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
"llilf\t{$dst, $src}",
[(set GR64:$dst, i64lo32:$src)]>;
def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
"llihf\t{$dst, $src}",
[(set GR64:$dst, i64hi32:$src)]>;
}
//===----------------------------------------------------------------------===//

51
test/CodeGen/SystemZ/01-RetImm.ll
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@ -1,6 +1,49 @@
; RUN: llvm-as < %s | llc -march=systemz
; RUN: llvm-as < %s | llc -march=systemz | grep lghi | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep llill | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep llilh | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep llihl | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep llihh | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep lgfi | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep llihf | count 1
define i64 @foo() {
define i64 @foo1() {
entry:
ret i64 0
}
ret i64 1
}
define i64 @foo2() {
entry:
ret i64 65535
}
define i64 @foo3() {
entry:
ret i64 131072
}
define i64 @foo4() {
entry:
ret i64 8589934592
}
define i64 @foo5() {
entry:
ret i64 562949953421312
}
define i64 @foo6() {
entry:
ret i64 65537
}
define i64 @foo7() {
entry:
ret i64 4294967295
}
define i64 @foo8() {
entry:
ret i64 281483566645248
}