6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-20 10:30:03 +00:00
Code Issues Projects Releases Wiki Activity

Generate code for llvm.uadd.with.overflow intrinsic. No conversion support yet.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59786 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2008-11-21 02:33:36 +00:00
parent cddd428459
commit da4948ac8c
1 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -4109,7 +4109,18 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
return 0;
}
case Intrinsic::uadd_with_overflow: {
// TODO: Convert to "ISD::UADDO" instruction.
// Convert to "ISD::UADDO" instruction.
SDValue Op1 = getValue(I.getOperand(1));
SDValue Op2 = getValue(I.getOperand(2));
MVT Ty = Op1.getValueType();
MVT ValueVTs[] = { Ty, MVT::i1 };
SDValue Ops[] = { Op1, Op2 };
SDValue Result = DAG.getNode(ISD::UADDO, DAG.getVTList(&ValueVTs[0], 2),
&Ops[0], 2);
setValue(&I, Result);
return 0;
}