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Sink feature IsThumb into MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134608 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -16,6 +16,12 @@
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// ARM Subtarget state.
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//
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def ModeThumb : SubtargetFeature<"thumb", "IsThumb", "true",
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"Thumb mode">;
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//===----------------------------------------------------------------------===//
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// ARM Subtarget features.
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@ -85,23 +91,23 @@ def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
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def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
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"Supports Multiprocessing extension">;
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// ARM architectures.
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// ARM ISAs.
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def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
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"ARM v4T">;
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"Support ARM v4T instructions">;
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def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
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"ARM v5T",
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"Support ARM v5T instructions",
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[HasV4TOps]>;
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def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
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"ARM v5TE, v5TEj, v5TExp",
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"Support ARM v5TE, v5TEj, and v5TExp instructions",
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[HasV5TOps]>;
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def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
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"ARM v6",
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"Support ARM v6 instructions",
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[HasV5TEOps]>;
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def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
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"ARM v6t2",
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"Support ARM v6t2 instructions",
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[HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
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def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
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"ARM v7",
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"Support ARM v7 instructions",
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[HasV6T2Ops]>;
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//===----------------------------------------------------------------------===//
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@ -111,8 +117,6 @@ def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
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include "ARMSchedule.td"
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// ARM processor families.
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def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", "Others",
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"One of the other ARM processor families">;
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def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
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"Cortex-A8 ARM processors",
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[FeatureSlowFPBrcc, FeatureNEONForFP,
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@ -81,14 +81,13 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
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// Insert the architecture feature derived from the target triple into the
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// feature string. This is important for setting features that are implied
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// based on the architecture version.
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std::string ArchFS = ARM_MC::ParseARMTriple(TT, IsThumb);
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std::string ArchFS = ARM_MC::ParseARMTriple(TT);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = ArchFS + "," + FS;
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else
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ArchFS = FS;
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}
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ParseSubtargetFeatures(CPUString, ArchFS);
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// Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
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@ -42,8 +42,16 @@ MCRegisterInfo *createARMMCRegisterInfo() {
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MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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std::string ArchFS = ARM_MC::ParseARMTriple(TT);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = ArchFS + "," + FS.str();
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else
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ArchFS = FS;
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}
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitARMMCSubtargetInfo(X, CPU, FS);
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InitARMMCSubtargetInfo(X, CPU, ArchFS);
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return X;
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}
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@ -74,16 +82,17 @@ extern "C" void LLVMInitializeARMMCSubtargetInfo() {
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createARMMCSubtargetInfo);
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}
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std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) {
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std::string ARM_MC::ParseARMTriple(StringRef TT) {
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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unsigned Len = TT.size();
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unsigned Idx = 0;
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bool isThumb = false;
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if (Len >= 5 && TT.substr(0, 4) == "armv")
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Idx = 4;
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else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
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IsThumb = true;
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isThumb = true;
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if (Len >= 7 && TT[5] == 'v')
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Idx = 6;
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}
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@ -116,5 +125,12 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, bool &IsThumb) {
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ARMArchFeature = "+v4t";
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}
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if (isThumb) {
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if (ARMArchFeature.empty())
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ARMArchFeature = "+thumb";
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else
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ARMArchFeature += ",+thumb";
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}
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return ARMArchFeature;
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}
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@ -23,7 +23,7 @@ class StringRef;
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extern Target TheARMTarget, TheThumbTarget;
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namespace ARM_MC {
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std::string ParseARMTriple(StringRef TT, bool &IsThumb);
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std::string ParseARMTriple(StringRef TT);
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}
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} // End llvm namespace
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