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Fix itins for VPAL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100658 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -516,11 +516,11 @@ def CortexA8Itineraries : ProcessorItineraries<[
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//
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// Double-register Integer Pair Add Long
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InstrItinData<IIC_VPALiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>,
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InstrStage<1, [FU_NPipe]>], [6, 3, 1]>,
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//
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// Quad-register Integer Pair Add Long
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InstrItinData<IIC_VPALiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>,
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InstrStage<2, [FU_NPipe]>], [7, 3, 1]>,
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//
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// Double-register Absolute Difference and Accumulate
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InstrItinData<IIC_VABAD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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@ -923,7 +923,21 @@ def CortexA9Itineraries : ProcessorItineraries<[
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// Extra 3 latency cycle since wbck is 6 cycles
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InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]>
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InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]>,
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//
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// Double-register Integer Pair Add Long
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InstrItinData<IIC_VPALiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
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// Extra 3 latency cycle since wbck is 6 cycles
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InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [6, 3, 1]>,
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//
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// Quad-register Integer Pair Add Long
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InstrItinData<IIC_VPALiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
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// Extra 3 latency cycle since wbck is 6 cycles
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InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<2, [FU_NPipe]>], [6, 3, 1]>
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]>;
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