6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-19 03:29:22 +00:00
Code Issues Projects Releases Wiki Activity

convert FP instructions to use an asmstring and operand list, allowing FP

Browse Source 
programs to work on V8 again


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24761 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-17 06:32:52 +00:00
parent 45f37bc527
commit dc6938ac23
4 changed files with 144 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Target/Sparc/SparcInstrFormats.td
View File

@ -89,12 +89,15 @@ class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
}
// floating-point
class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, string name> : F3 {
class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
string asmstr> : F3 {
bits<5> rs2;
dag OperandList = ops;
let AsmString = asmstr;
let op = opVal;
let op3 = op3val;
let Name = name;
let Inst{13-5} = opfval; // fp opcode
let Inst{4-0} = rs2;

93
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -452,44 +452,85 @@ def WRri : F3_2<2, 0b110000,
"wr $b, $c, $dst">;
// Convert Integer to Floating-point Instructions, p. 141
def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">;
def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">;
def FITOS : F3_3<2, 0b110100, 0b011000100,
(ops FPRegs:$dst, FPRegs:$src),
"fitos $src, $dst">;
def FITOD : F3_3<2, 0b110100, 0b011001000,
(ops DFPRegs:$dst, DFPRegs:$src),
"fitod $src, $dst">;
// Convert Floating-point to Integer Instructions, p. 142
def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">;
def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">;
def FSTOI : F3_3<2, 0b110100, 0b011010001,
(ops FPRegs:$dst, FPRegs:$src),
"fstoi $src, $dst">;
def FDTOI : F3_3<2, 0b110100, 0b011010010,
(ops DFPRegs:$dst, DFPRegs:$src),
"fdtoi $src, $dst">;
// Convert between Floating-point Formats Instructions, p. 143
def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">;
def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">;
def FSTOD : F3_3<2, 0b110100, 0b011001001,
(ops DFPRegs:$dst, FPRegs:$src),
"fstod $src, $dst">;
def FDTOS : F3_3<2, 0b110100, 0b011000110,
(ops FPRegs:$dst, DFPRegs:$src),
"fdtos $src, $dst">;
// Floating-point Move Instructions, p. 144
def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">;
def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">;
def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">;
def FMOVS : F3_3<2, 0b110100, 0b000000001,
(ops FPRegs:$dst, FPRegs:$src),
"fmovs $src, $dst">;
def FNEGS : F3_3<2, 0b110100, 0b000000101,
(ops FPRegs:$dst, FPRegs:$src),
"fnegs $src, $dst">;
def FABSS : F3_3<2, 0b110100, 0b000001001,
(ops FPRegs:$dst, FPRegs:$src),
"fabss $src, $dst">;
// Floating-point Add and Subtract Instructions, p. 146
def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">;
def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">;
def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">;
def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">;
def FADDS : F3_3<2, 0b110100, 0b001000001,
(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
"fadds $src1, $src2, $dst">;
def FADDD : F3_3<2, 0b110100, 0b001000010,
(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
"faddd $src1, $src2, $dst">;
def FSUBS : F3_3<2, 0b110100, 0b001000101,
(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
"fsubs $src1, $src2, $dst">;
def FSUBD : F3_3<2, 0b110100, 0b001000110,
(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
"fsubd $src1, $src2, $dst">;
// Floating-point Multiply and Divide Instructions, p. 147
def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">;
def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">;
def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">;
def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">;
def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">;
def FMULS : F3_3<2, 0b110100, 0b001001001,
(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
"fmuls $src1, $src2, $dst">;
def FMULD : F3_3<2, 0b110100, 0b001001010,
(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
"fmuld $src1, $src2, $dst">;
def FSMULD : F3_3<2, 0b110100, 0b001101001,
(ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
"fsmuld $src1, $src2, $dst">;
def FDIVS : F3_3<2, 0b110100, 0b001001101,
(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
"fdivs $src1, $src2, $dst">;
def FDIVD : F3_3<2, 0b110100, 0b001001110,
(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
"fdivd $src1, $src2, $dst">;
// Floating-point Compare Instructions, p. 148
// Note: the 2nd template arg is different for these guys.
// Note 2: the result of a FCMP is not available until the 2nd cycle
// after the instr is retired, but there is no interlock. This behavior
// is modelled as a delay slot.
let hasDelaySlot = 1 in {
def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
}
// is modelled with a forced noop after the instruction.
def FCMPS : F3_3<2, 0b110101, 0b001010001,
(ops FPRegs:$src1, FPRegs:$src2),
"fcmps $src1, $src2\n nop">;
def FCMPD : F3_3<2, 0b110101, 0b001010010,
(ops DFPRegs:$src1, DFPRegs:$src2),
"fcmpd $src1, $src2\n nop">;
def FCMPES : F3_3<2, 0b110101, 0b001010101,
(ops FPRegs:$src1, FPRegs:$src2),
"fcmpes $src1, $src2\n nop">;
def FCMPED : F3_3<2, 0b110101, 0b001010110,
(ops DFPRegs:$src1, DFPRegs:$src2),
"fcmped $src1, $src2\n nop">;

7
lib/Target/SparcV8/SparcV8InstrFormats.td
View File

@ -89,12 +89,15 @@ class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
}
// floating-point
class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, string name> : F3 {
class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
string asmstr> : F3 {
bits<5> rs2;
dag OperandList = ops;
let AsmString = asmstr;
let op = opVal;
let op3 = op3val;
let Name = name;
let Inst{13-5} = opfval; // fp opcode
let Inst{4-0} = rs2;

93
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -452,44 +452,85 @@ def WRri : F3_2<2, 0b110000,
"wr $b, $c, $dst">;
// Convert Integer to Floating-point Instructions, p. 141
def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">;
def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">;
def FITOS : F3_3<2, 0b110100, 0b011000100,
(ops FPRegs:$dst, FPRegs:$src),
"fitos $src, $dst">;
def FITOD : F3_3<2, 0b110100, 0b011001000,
(ops DFPRegs:$dst, DFPRegs:$src),
"fitod $src, $dst">;
// Convert Floating-point to Integer Instructions, p. 142
def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">;
def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">;
def FSTOI : F3_3<2, 0b110100, 0b011010001,
(ops FPRegs:$dst, FPRegs:$src),
"fstoi $src, $dst">;
def FDTOI : F3_3<2, 0b110100, 0b011010010,
(ops DFPRegs:$dst, DFPRegs:$src),
"fdtoi $src, $dst">;
// Convert between Floating-point Formats Instructions, p. 143
def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">;
def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">;
def FSTOD : F3_3<2, 0b110100, 0b011001001,
(ops DFPRegs:$dst, FPRegs:$src),
"fstod $src, $dst">;
def FDTOS : F3_3<2, 0b110100, 0b011000110,
(ops FPRegs:$dst, DFPRegs:$src),
"fdtos $src, $dst">;
// Floating-point Move Instructions, p. 144
def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">;
def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">;
def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">;
def FMOVS : F3_3<2, 0b110100, 0b000000001,
(ops FPRegs:$dst, FPRegs:$src),
"fmovs $src, $dst">;
def FNEGS : F3_3<2, 0b110100, 0b000000101,
(ops FPRegs:$dst, FPRegs:$src),
"fnegs $src, $dst">;
def FABSS : F3_3<2, 0b110100, 0b000001001,
(ops FPRegs:$dst, FPRegs:$src),
"fabss $src, $dst">;
// Floating-point Add and Subtract Instructions, p. 146
def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">;
def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">;
def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">;
def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">;
def FADDS : F3_3<2, 0b110100, 0b001000001,
(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
"fadds $src1, $src2, $dst">;
def FADDD : F3_3<2, 0b110100, 0b001000010,
(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
"faddd $src1, $src2, $dst">;
def FSUBS : F3_3<2, 0b110100, 0b001000101,
(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
"fsubs $src1, $src2, $dst">;
def FSUBD : F3_3<2, 0b110100, 0b001000110,
(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
"fsubd $src1, $src2, $dst">;
// Floating-point Multiply and Divide Instructions, p. 147
def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">;
def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">;
def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">;
def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">;
def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">;
def FMULS : F3_3<2, 0b110100, 0b001001001,
(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
"fmuls $src1, $src2, $dst">;
def FMULD : F3_3<2, 0b110100, 0b001001010,
(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
"fmuld $src1, $src2, $dst">;
def FSMULD : F3_3<2, 0b110100, 0b001101001,
(ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
"fsmuld $src1, $src2, $dst">;
def FDIVS : F3_3<2, 0b110100, 0b001001101,
(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
"fdivs $src1, $src2, $dst">;
def FDIVD : F3_3<2, 0b110100, 0b001001110,
(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
"fdivd $src1, $src2, $dst">;
// Floating-point Compare Instructions, p. 148
// Note: the 2nd template arg is different for these guys.
// Note 2: the result of a FCMP is not available until the 2nd cycle
// after the instr is retired, but there is no interlock. This behavior
// is modelled as a delay slot.
let hasDelaySlot = 1 in {
def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
}
// is modelled with a forced noop after the instruction.
def FCMPS : F3_3<2, 0b110101, 0b001010001,
(ops FPRegs:$src1, FPRegs:$src2),
"fcmps $src1, $src2\n nop">;
def FCMPD : F3_3<2, 0b110101, 0b001010010,
(ops DFPRegs:$src1, DFPRegs:$src2),
"fcmpd $src1, $src2\n nop">;
def FCMPES : F3_3<2, 0b110101, 0b001010101,
(ops FPRegs:$src1, FPRegs:$src2),
"fcmpes $src1, $src2\n nop">;
def FCMPED : F3_3<2, 0b110101, 0b001010110,
(ops DFPRegs:$src1, DFPRegs:$src2),
"fcmped $src1, $src2\n nop">;