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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
hasFP() is now a virtual method of MRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -367,6 +367,11 @@ public:
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return 0;
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}
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/// hasFP - Return true if the specified function should have a dedicated frame
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/// pointer register. For most targets this is true only if the function has
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/// variable sized allocas or if frame pointer elimination is disabled.
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virtual bool hasFP(const MachineFunction &MF) const = 0;
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/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
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/// frame setup/destroy instructions if they exist (-1 otherwise). Some
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/// targets use pseudo instructions in order to abstract away the difference
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@ -277,7 +277,7 @@ ARMRegisterInfo::getCalleeSavedRegClasses() const {
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/// pointer register. This is true if the function has variable sized allocas
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/// or if frame pointer elimination is disabled.
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///
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static bool hasFP(const MachineFunction &MF) {
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bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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@ -68,6 +68,8 @@ public:
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const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
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bool hasFP(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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@ -150,6 +150,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
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GPRClass::iterator
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GPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo *RI = TM.getRegisterInfo();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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GPRClass::iterator I;
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if (Subtarget.isThumb())
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@ -167,7 +168,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
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}
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// Mac OS X requires FP not to be clobbered for backtracing purpose.
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return (Subtarget.isTargetDarwin() || hasFP(MF)) ? I-1 : I;
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return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
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}
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}];
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}
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@ -186,7 +186,7 @@ AlphaRegisterInfo::getCalleeSavedRegClasses() const {
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(const MachineFunction &MF) {
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bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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return MFI->hasVarSizedObjects();
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}
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@ -49,6 +49,8 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
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const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
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bool hasFP(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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@ -114,7 +114,7 @@ IA64RegisterInfo::getCalleeSavedRegClasses() const {
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(const MachineFunction &MF) {
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bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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@ -48,6 +48,8 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
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const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
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bool hasFP(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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@ -410,7 +410,7 @@ static bool needsFP(const MachineFunction &MF) {
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// hasFP - Return true if the specified function actually has a dedicated frame
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// pointer register. This is true if the function needs a frame pointer and has
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// a non-zero stack size.
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static bool hasFP(const MachineFunction &MF) {
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bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return MFI->getStackSize() && needsFP(MF);
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}
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@ -58,6 +58,8 @@ public:
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const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
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bool hasFP(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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@ -122,6 +122,9 @@ SparcRegisterInfo::getCalleeSavedRegClasses() const {
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return CalleeSavedRegClasses;
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}
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bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
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return false;
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}
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void SparcRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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@ -52,6 +52,8 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
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const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
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bool hasFP(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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@ -891,7 +891,7 @@ X86RegisterInfo::getCalleeSavedRegClasses() const {
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(const MachineFunction &MF) {
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bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
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return (NoFramePointerElim ||
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MF.getFrameInfo()->hasVarSizedObjects() ||
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MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
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@ -998,7 +998,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = MFI->getStackSize();
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if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
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if (MFI->hasCalls() || MFI->hasVarSizedObjects()) {
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// When we have no frame pointer, we reserve argument space for call sites
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// in the function immediately on entry to the current function. This
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// eliminates the need for add/sub ESP brackets around call sites.
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@ -78,6 +78,8 @@ public:
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/// length of this list match the getCalleeSavedRegs() list.
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const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
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bool hasFP(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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@ -197,10 +197,11 @@ def GR8 : RegisterClass<"X86", [i8], 8,
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GR8Class::iterator
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GR8Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (!Subtarget.is64Bit())
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return X86_GR8_AO_32;
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else if (hasFP(MF))
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else if (RI->hasFP(MF))
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return X86_GR8_AO_64_fp;
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else
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return X86_GR8_AO_64;
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@ -209,10 +210,11 @@ def GR8 : RegisterClass<"X86", [i8], 8,
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GR8Class::iterator
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GR8Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (!Subtarget.is64Bit())
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return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
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else if (hasFP(MF))
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else if (RI->hasFP(MF))
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return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
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else
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return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
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@ -248,14 +250,15 @@ def GR16 : RegisterClass<"X86", [i16], 16,
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GR16Class::iterator
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GR16Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit()) {
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if (hasFP(MF))
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if (RI->hasFP(MF))
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return X86_GR16_AO_64_fp;
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else
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return X86_GR16_AO_64;
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} else {
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if (hasFP(MF))
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if (RI->hasFP(MF))
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return X86_GR16_AO_32_fp;
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else
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return X86_GR16_AO_32;
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@ -265,14 +268,15 @@ def GR16 : RegisterClass<"X86", [i16], 16,
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GR16Class::iterator
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GR16Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit()) {
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if (hasFP(MF))
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if (RI->hasFP(MF))
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return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
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else
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return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
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} else {
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if (hasFP(MF))
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if (RI->hasFP(MF))
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return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
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else
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return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
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@ -309,14 +313,15 @@ def GR32 : RegisterClass<"X86", [i32], 32,
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GR32Class::iterator
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GR32Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit()) {
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if (hasFP(MF))
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if (RI->hasFP(MF))
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return X86_GR32_AO_64_fp;
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else
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return X86_GR32_AO_64;
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} else {
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if (hasFP(MF))
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if (RI->hasFP(MF))
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return X86_GR32_AO_32_fp;
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else
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return X86_GR32_AO_32;
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@ -326,14 +331,15 @@ def GR32 : RegisterClass<"X86", [i32], 32,
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GR32Class::iterator
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GR32Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit()) {
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if (hasFP(MF))
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if (RI->hasFP(MF))
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return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
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else
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return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
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} else {
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if (hasFP(MF))
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if (RI->hasFP(MF))
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return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
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else
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return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
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@ -352,7 +358,9 @@ def GR64 : RegisterClass<"X86", [i64], 64,
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let MethodBodies = [{
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GR64Class::iterator
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GR64Class::allocation_order_end(const MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
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return end()-2; // If so, don't allocate RSP or RBP
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else
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return end()-1; // If not, just don't allocate RSP
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