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Fix a bug where we incorrectly turned '(X & 0) == 0' into '(X & 0) >> -1',

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which is undefined.  "0" isn't a power of 2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30947 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-10-13 22:46:18 +00:00
parent c50e2bcdf7
commit dc78cbf457
1 changed files with 2 additions and 2 deletions
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4
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -910,7 +910,7 @@ SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,
dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
// Perform the xform if the AND RHS is a single bit.
if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
if (isPowerOf2_64(AndRHS->getValue())) {
return getNode(ISD::SRL, VT, N1,
getConstant(Log2_64(AndRHS->getValue()),
TLI.getShiftAmountTy()));
@ -918,7 +918,7 @@ SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,
} else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) {
// (X & 8) == 8 --> (X & 8) >> 3
// Perform the xform if C2 is a single bit.
if ((C2 & (C2-1)) == 0) {
if (isPowerOf2_64(C2)) {
return getNode(ISD::SRL, VT, N1,
getConstant(Log2_64(C2),TLI.getShiftAmountTy()));
}