mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
Patch up omissions in DebugLoc propagation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63693 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
parent
c460ae9001
commit
dd64c417c0
@ -1288,7 +1288,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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std::swap(N0, N1);
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}
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SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
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SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
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N0, SDValue()).getValue(1);
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if (foldedLoad) {
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@ -1305,7 +1305,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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// Copy the low half of the result, if it is needed.
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if (!N.getValue(0).use_empty()) {
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SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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LoReg, NVT, InFlag);
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InFlag = Result.getValue(2);
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ReplaceUses(N.getValue(0), Result);
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@ -1321,7 +1321,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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if (HiReg == X86::AH && Subtarget->is64Bit()) {
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// Prevent use of AH in a REX instruction by referencing AX instead.
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// Shift it down 8 bits.
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Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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X86::AX, MVT::i16, InFlag);
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InFlag = Result.getValue(2);
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Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
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@ -1332,7 +1332,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
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MVT::i8, Result, SRIdx), 0);
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} else {
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Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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HiReg, NVT, InFlag);
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InFlag = Result.getValue(2);
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}
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@ -1421,11 +1421,11 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
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Chain = CurDAG->getEntryNode();
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}
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Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue());
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Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
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InFlag = Chain.getValue(1);
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} else {
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InFlag =
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CurDAG->getCopyToReg(CurDAG->getEntryNode(),
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CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
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LoReg, N0, SDValue()).getValue(1);
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if (isSigned && !signBitIsZero) {
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// Sign extend the low part into the high part.
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@ -1435,7 +1435,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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// Zero out the high part, effectively zero extending the input.
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SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT),
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0);
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InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg,
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InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, HiReg,
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ClrNode, InFlag).getValue(1);
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}
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}
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@ -1454,7 +1454,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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// Copy the division (low) result, if it is needed.
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if (!N.getValue(0).use_empty()) {
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SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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LoReg, NVT, InFlag);
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InFlag = Result.getValue(2);
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ReplaceUses(N.getValue(0), Result);
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@ -1470,7 +1470,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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if (HiReg == X86::AH && Subtarget->is64Bit()) {
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// Prevent use of AH in a REX instruction by referencing AX instead.
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// Shift it down 8 bits.
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Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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X86::AX, MVT::i16, InFlag);
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InFlag = Result.getValue(2);
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Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
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@ -1482,7 +1482,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) {
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Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
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MVT::i8, Result, SRIdx), 0);
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} else {
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Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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HiReg, NVT, InFlag);
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InFlag = Result.getValue(2);
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}
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@ -987,7 +987,7 @@ SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
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continue;
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}
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Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
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Flag = Chain.getValue(1);
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}
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@ -1004,9 +1004,9 @@ SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
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Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
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FuncInfo->setSRetReturnReg(Reg);
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}
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SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
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SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
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Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
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Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
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Flag = Chain.getValue(1);
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}
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@ -1060,7 +1060,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
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CopyVT = MVT::f80;
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}
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Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
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Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
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CopyVT, InFlag).getValue(1);
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SDValue Val = Chain.getValue(0);
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InFlag = Chain.getValue(2);
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@ -1199,9 +1199,10 @@ X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
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/// function parameter.
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static SDValue
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CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
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ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
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ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
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DebugLoc dl) {
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SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
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return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
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return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
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/*AlwaysInline=*/true, NULL, 0, NULL, 0);
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}
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@ -1302,7 +1303,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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}
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unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
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SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
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SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
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// If this is an 8 or 16-bit value, it is really passed promoted to 32
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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@ -1346,7 +1347,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
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FuncInfo->setSRetReturnReg(Reg);
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}
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SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
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SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
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Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
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}
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@ -1417,7 +1418,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
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unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
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X86::GR64RegisterClass);
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SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
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SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
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SDValue Store =
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DAG.getStore(Val.getValue(1), dl, Val, FIN,
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PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
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@ -1432,7 +1433,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
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for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
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unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
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X86::VR128RegisterClass);
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SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
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SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
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SDValue Store =
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DAG.getStore(Val.getValue(1), dl, Val, FIN,
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PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
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@ -1484,7 +1485,7 @@ X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
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SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
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PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
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if (Flags.isByVal()) {
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return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
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return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
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}
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return DAG.getStore(Chain, dl, Arg, PtrOff,
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PseudoSourceValue::getStack(), LocMemOffset);
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@ -1633,7 +1634,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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if (!IsTailCall || (IsTailCall && isByVal)) {
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assert(VA.isMemLoc());
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if (StackPtr.getNode() == 0)
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StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
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StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
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MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
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Chain, Arg, Flags));
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@ -1652,15 +1653,15 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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// tail call optimization the copies to registers are lowered later.
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if (!IsTailCall)
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
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InFlag);
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Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
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RegsToPass[i].second, InFlag);
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InFlag = Chain.getValue(1);
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}
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// ELF / PIC requires GOT in the EBX register before function calls via PLT
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// GOT pointer.
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if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
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Chain = DAG.getCopyToReg(Chain, X86::EBX,
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Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
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DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
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InFlag);
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InFlag = Chain.getValue(1);
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@ -1700,7 +1701,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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assert((Subtarget->hasSSE1() || !NumXMMRegs)
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&& "SSE registers cannot be used when SSE is disabled");
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Chain = DAG.getCopyToReg(Chain, X86::AL,
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Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
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DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
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InFlag = Chain.getValue(1);
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}
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@ -1729,11 +1730,12 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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// Copy relative to framepointer.
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SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
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if (StackPtr.getNode() == 0)
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StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
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StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
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getPointerTy());
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Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
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MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
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Flags, DAG));
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Flags, DAG, dl));
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} else {
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// Store relative to framepointer.
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MemOpChains2.push_back(
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@ -1749,8 +1751,8 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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// Copy arguments to their registers.
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
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InFlag);
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Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
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RegsToPass[i].second, InFlag);
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InFlag = Chain.getValue(1);
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}
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InFlag =SDValue();
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@ -1774,7 +1776,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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} else if (IsTailCall) {
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unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
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Chain = DAG.getCopyToReg(Chain,
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Chain = DAG.getCopyToReg(Chain, dl,
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DAG.getRegister(Opc, getPointerTy()),
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Callee,InFlag);
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Callee = DAG.getRegister(Opc, getPointerTy());
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@ -4577,7 +4579,8 @@ static SDValue
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LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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const MVT PtrVT) {
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SDValue InFlag;
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SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
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DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
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SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
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DAG.getNode(X86ISD::GlobalBaseReg,
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PtrVT), InFlag);
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InFlag = Chain.getValue(1);
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@ -4594,7 +4597,7 @@ LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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// call ___tls_get_addr. This function receives its argument in
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// the register EAX.
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Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
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Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Result, InFlag);
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InFlag = Chain.getValue(1);
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NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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@ -4607,7 +4610,7 @@ LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
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InFlag = Chain.getValue(1);
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return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
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return DAG.getCopyFromReg(Chain, dl, X86::EAX, PtrVT, InFlag);
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}
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// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
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@ -4615,6 +4618,7 @@ static SDValue
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LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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const MVT PtrVT) {
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SDValue InFlag, Chain;
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DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
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// emit leaq symbol@TLSGD(%rip), %rdi
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SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
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@ -4628,7 +4632,7 @@ LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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// call __tls_get_addr. This function receives its argument in
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// the register RDI.
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Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
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Chain = DAG.getCopyToReg(Chain, dl, X86::RDI, Result, InFlag);
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InFlag = Chain.getValue(1);
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NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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@ -4640,7 +4644,7 @@ LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
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InFlag = Chain.getValue(1);
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return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
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return DAG.getCopyFromReg(Chain, dl, X86::RAX, PtrVT, InFlag);
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}
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// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
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@ -5586,7 +5590,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
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Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
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Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
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Flag = Chain.getValue(1);
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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@ -5603,7 +5607,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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DAG.getIntPtrConstant(0, true),
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Flag);
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Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
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Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
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SDValue Ops1[2] = { Chain.getValue(0), Chain };
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return DAG.getMergeValues(Ops1, 2, dl);
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@ -5897,8 +5901,9 @@ SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
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SDValue SrcPtr = Op.getOperand(2);
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const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
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const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
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DebugLoc dl = Op.getNode()->getDebugLoc();
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return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
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return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
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DAG.getIntPtrConstant(24), 8, false,
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DstSV, 0, SrcSV, 0);
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}
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@ -6125,11 +6130,12 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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MFI->setFrameAddressIsTaken(true);
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MVT VT = Op.getValueType();
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DebugLoc dl = Op.getNode()->getDebugLoc(); // FIXME probably not meaningful
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unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
|
||||
unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
|
||||
SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT);
|
||||
SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
|
||||
while (Depth--)
|
||||
FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0);
|
||||
FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
|
||||
return FrameAddr;
|
||||
}
|
||||
|
||||
@ -6154,7 +6160,7 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
|
||||
DAG.getIntPtrConstant(-TD->getPointerSize()));
|
||||
StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
|
||||
Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
|
||||
Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
|
||||
Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
|
||||
MF.getRegInfo().addLiveOut(StoreAddrReg);
|
||||
|
||||
return DAG.getNode(X86ISD::EH_RETURN, dl,
|
||||
@ -6539,7 +6545,7 @@ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
|
||||
Reg = X86::RAX; size = 8;
|
||||
break;
|
||||
}
|
||||
SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
|
||||
SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
|
||||
Op.getOperand(2), SDValue());
|
||||
SDValue Ops[] = { cpIn.getValue(0),
|
||||
Op.getOperand(1),
|
||||
@ -6549,7 +6555,7 @@ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
|
||||
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
||||
SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
|
||||
SDValue cpOut =
|
||||
DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
|
||||
DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
|
||||
return cpOut;
|
||||
}
|
||||
|
||||
@ -6560,8 +6566,8 @@ SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
|
||||
SDValue TheChain = Op.getOperand(0);
|
||||
DebugLoc dl = Op.getNode()->getDebugLoc();
|
||||
SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
|
||||
SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
|
||||
SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64,
|
||||
SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
|
||||
SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
|
||||
rax.getValue(2));
|
||||
SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
|
||||
DAG.getConstant(32, MVT::i8));
|
||||
@ -6692,8 +6698,9 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
|
||||
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
||||
SDValue TheChain = N->getOperand(0);
|
||||
SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
|
||||
SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
|
||||
SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32,
|
||||
SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
|
||||
rd.getValue(1));
|
||||
SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
|
||||
eax.getValue(2));
|
||||
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
|
||||
SDValue Ops[] = { eax, edx };
|
||||
@ -6709,27 +6716,27 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
|
||||
DAG.getConstant(0, MVT::i32));
|
||||
cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
|
||||
DAG.getConstant(1, MVT::i32));
|
||||
cpInL = DAG.getCopyToReg(N->getOperand(0), X86::EAX, cpInL, SDValue());
|
||||
cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH,
|
||||
cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
|
||||
cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
|
||||
cpInL.getValue(1));
|
||||
SDValue swapInL, swapInH;
|
||||
swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
|
||||
DAG.getConstant(0, MVT::i32));
|
||||
swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
|
||||
DAG.getConstant(1, MVT::i32));
|
||||
swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, swapInL,
|
||||
swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
|
||||
cpInH.getValue(1));
|
||||
swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, swapInH,
|
||||
swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
|
||||
swapInL.getValue(1));
|
||||
SDValue Ops[] = { swapInH.getValue(0),
|
||||
N->getOperand(1),
|
||||
swapInH.getValue(1) };
|
||||
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
|
||||
SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
|
||||
SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
|
||||
Result.getValue(1));
|
||||
SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
|
||||
cpOutL.getValue(2));
|
||||
SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
|
||||
MVT::i32, Result.getValue(1));
|
||||
SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
|
||||
MVT::i32, cpOutL.getValue(2));
|
||||
SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
|
||||
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
|
||||
Results.push_back(cpOutH.getValue(1));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user