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Reverting r181331.
Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181334 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -37,8 +37,6 @@ namespace llvm {
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FunctionPass *createHexagonCFGOptimizer(const HexagonTargetMachine &TM);
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FunctionPass *createHexagonSplitTFRCondSets(const HexagonTargetMachine &TM);
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FunctionPass *createHexagonSplitConst32AndConst64(
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const HexagonTargetMachine &TM);
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FunctionPass *createHexagonExpandPredSpillCode(
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const HexagonTargetMachine &TM);
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FunctionPass *createHexagonHardwareLoops();
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@ -948,6 +948,7 @@ HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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SDValue
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HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
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EVT ValTy = Op.getValueType();
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DebugLoc dl = Op.getDebugLoc();
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ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
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SDValue Res;
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@ -1,176 +0,0 @@
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//=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// When the compiler is invoked with no small data, for instance, with the -G0
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// command line option, then all CONST32_* opcodes should be broken down into
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// appropriate LO and HI instructions. This splitting is done by this pass.
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// The only reason this is not done in the DAG lowering itself is that there
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// is no simple way of getting the register allocator to allot the same hard
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// register to the result of LO and HI instructions. This pass is always
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// scheduled after register allocation.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "xfer"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "HexagonTargetMachine.h"
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#include "HexagonSubtarget.h"
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#include "HexagonMachineFunctionInfo.h"
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#include <map>
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#include <iostream>
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#include "llvm/Support/CommandLine.h"
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#define DEBUG_TYPE "xfer"
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using namespace llvm;
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namespace {
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class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
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const HexagonTargetMachine& QTM;
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const HexagonSubtarget &QST;
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public:
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static char ID;
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HexagonSplitConst32AndConst64(const HexagonTargetMachine& TM)
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: MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
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const char *getPassName() const {
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return "Hexagon Split Const32s and Const64s";
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}
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bool runOnMachineFunction(MachineFunction &Fn);
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};
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char HexagonSplitConst32AndConst64::ID = 0;
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bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
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const TargetInstrInfo *TII = QTM.getInstrInfo();
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// Loop over all of the basic blocks
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for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
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MBBb != MBBe; ++MBBb) {
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MachineBasicBlock* MBB = MBBb;
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// Traverse the basic block
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MachineBasicBlock::iterator MII = MBB->begin();
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MachineBasicBlock::iterator MIE = MBB->end ();
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while (MII != MIE) {
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MachineInstr *MI = MII;
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int Opc = MI->getOpcode();
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if (Opc == Hexagon::CONST32_set) {
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int DestReg = MI->getOperand(0).getReg();
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MachineOperand &Symbol = MI->getOperand (1);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
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// MBB->erase returns the iterator to the next instruction, which is the
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// one we want to process next
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MII = MBB->erase (MI);
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continue;
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}
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else if (Opc == Hexagon::CONST32_set_jt) {
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int DestReg = MI->getOperand(0).getReg();
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MachineOperand &Symbol = MI->getOperand (1);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
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// MBB->erase returns the iterator to the next instruction, which is the
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// one we want to process next
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MII = MBB->erase (MI);
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continue;
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}
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else if (Opc == Hexagon::CONST32_Label) {
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int DestReg = MI->getOperand(0).getReg();
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MachineOperand &Symbol = MI->getOperand (1);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
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// MBB->erase returns the iterator to the next instruction, which is the
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// one we want to process next
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MII = MBB->erase (MI);
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continue;
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}
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else if (Opc == Hexagon::CONST32_Int_Real) {
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int DestReg = MI->getOperand(0).getReg();
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int64_t ImmValue = MI->getOperand(1).getImm ();
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LOi), DestReg).addImm(ImmValue);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
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MII = MBB->erase (MI);
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continue;
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}
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else if (Opc == Hexagon::CONST64_Int_Real) {
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int DestReg = MI->getOperand(0).getReg();
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int64_t ImmValue = MI->getOperand(1).getImm ();
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unsigned DestLo =
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QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_loreg);
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unsigned DestHi =
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QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_hireg);
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int32_t LowWord = (ImmValue & 0xFFFFFFFF);
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int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
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// Lower Registers Lower Half
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LOi), DestLo).addImm(LowWord);
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// Lower Registers Higher Half
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HIi), DestLo).addImm(LowWord);
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// Higher Registers Lower Half
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LOi), DestHi).addImm(HighWord);
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// Higher Registers Higher Half.
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HIi), DestHi).addImm(HighWord);
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MII = MBB->erase (MI);
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continue;
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}
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++MII;
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}
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}
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return true;
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}
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}
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//===----------------------------------------------------------------------===//
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// Public Constructor Functions
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//===----------------------------------------------------------------------===//
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FunctionPass *
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llvm::createHexagonSplitConst32AndConst64(const HexagonTargetMachine &TM) {
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return new HexagonSplitConst32AndConst64(TM);
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}
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@ -15,7 +15,6 @@
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#include "Hexagon.h"
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#include "HexagonISelLowering.h"
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#include "HexagonMachineScheduler.h"
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#include "HexagonTargetObjectFile.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Module.h"
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#include "llvm/PassManager.h"
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@ -157,17 +156,9 @@ bool HexagonPassConfig::addPostRegAlloc() {
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}
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bool HexagonPassConfig::addPreSched2() {
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const HexagonTargetMachine &TM = getHexagonTargetMachine();
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HexagonTargetObjectFile &TLOF =
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(HexagonTargetObjectFile&)(getTargetLowering()->getObjFileLowering());
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if (getOptLevel() != CodeGenOpt::None)
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addPass(&IfConverterID);
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if (!TLOF.IsSmallDataEnabled()) {
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addPass(createHexagonSplitConst32AndConst64(TM));
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printAndVerify("After hexagon split const32/64 pass");
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}
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return true;
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return false;
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}
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bool HexagonPassConfig::addPreEmitPass() {
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@ -25,8 +25,7 @@
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using namespace llvm;
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static cl::opt<int> SmallDataThreshold("hexagon-small-data-threshold",
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cl::init(8), cl::Hidden,
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cl::desc("The maximum size of an object in the sdata section"));
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cl::init(8), cl::Hidden);
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void HexagonTargetObjectFile::Initialize(MCContext &Ctx,
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const TargetMachine &TM) {
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@ -47,11 +46,6 @@ void HexagonTargetObjectFile::Initialize(MCContext &Ctx,
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static bool IsInSmallSection(uint64_t Size) {
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return Size > 0 && Size <= (uint64_t)SmallDataThreshold;
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}
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bool HexagonTargetObjectFile::IsSmallDataEnabled () const {
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return SmallDataThreshold > 0;
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}
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/// IsGlobalInSmallSection - Return true if this global value should be
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/// placed into small data/bss section.
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bool HexagonTargetObjectFile::IsGlobalInSmallSection(const GlobalValue *GV,
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bool IsGlobalInSmallSection(const GlobalValue *GV,
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const TargetMachine &TM) const;
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bool IsSmallDataEnabled () const;
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const MCSection* SelectSectionForGlobal(const GlobalValue *GV,
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SectionKind Kind,
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Mangler *Mang,
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@ -1,26 +0,0 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-small-data-threshold=0 < %s | FileCheck %s
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; Check that CONST32/CONST64 instructions are 'not' generated when
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; small-data-threshold is set to 0.
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; with immediate value.
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@a = external global i32
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@b = external global i32
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@la = external global i64
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@lb = external global i64
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define void @test1() nounwind {
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; CHECK-NOT: CONST32
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entry:
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store i32 12345670, i32* @a, align 4
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store i32 12345670, i32* @b, align 4
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ret void
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}
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define void @test2() nounwind {
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; CHECK-NOT: CONST64
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entry:
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store i64 1234567890123, i64* @la, align 8
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store i64 1234567890123, i64* @lb, align 8
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ret void
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}
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