mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-06-09 23:29:52 +00:00
Build system infrastructure for multiple tblgens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Peter Collingbourne
parent
930193cb55
commit
de8f33c199
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@ -187,6 +187,10 @@ endif( ${CMAKE_SYSTEM_NAME} MATCHES SunOS )
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include(AddLLVM)
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include(TableGen)
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macro(llvm_tablegen)
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tablegen(LLVM ${ARGN})
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endmacro()
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if( MINGW )
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# People report that -O3 is unreliable on MinGW. The traditional
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# build also uses -O2 for that reason:
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@ -197,18 +201,8 @@ endif()
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add_subdirectory(lib/Support)
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add_subdirectory(lib/TableGen)
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set(LLVM_TABLEGEN "tblgen" CACHE
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STRING "Native TableGen executable. Saves building one when cross-compiling.")
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# Effective tblgen executable to be used:
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set(LLVM_TABLEGEN_EXE ${LLVM_TABLEGEN})
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add_subdirectory(utils/TableGen)
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if( CMAKE_CROSSCOMPILING )
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# This adds a dependency on target `tblgen', so must go after utils/TableGen
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include( CrossCompileLLVM )
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endif( CMAKE_CROSSCOMPILING )
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add_subdirectory(include/llvm)
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add_subdirectory(lib)
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@ -450,11 +450,11 @@ Echo = @$(EchoCmd)
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ifndef LLVMAS
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LLVMAS := $(LLVMToolDir)/llvm-as$(EXEEXT)
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endif
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ifndef TBLGEN
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ifndef LLVM_TBLGEN
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ifeq ($(LLVM_CROSS_COMPILING),1)
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TBLGEN := $(BuildLLVMToolDir)/tblgen$(BUILD_EXEEXT)
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LLVM_TBLGEN := $(BuildLLVMToolDir)/llvm-tblgen$(BUILD_EXEEXT)
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else
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TBLGEN := $(LLVMToolDir)/tblgen$(EXEEXT)
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LLVM_TBLGEN := $(LLVMToolDir)/llvm-tblgen$(EXEEXT)
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endif
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endif
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LLVM_CONFIG := $(LLVMToolDir)/llvm-config
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@ -684,10 +684,11 @@ DataInstall = $(INSTALL) -m 0644
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# When compiling under Mingw/Cygwin, the tblgen tool expects Windows
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# paths. In this case, the SYSPATH function (defined in
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# Makefile.config) transforms Unix paths into Windows paths.
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TableGen = $(TBLGEN) -I $(call SYSPATH, $(PROJ_SRC_DIR)) \
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TableGen.Flags= -I $(call SYSPATH, $(PROJ_SRC_DIR)) \
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-I $(call SYSPATH, $(LLVM_SRC_ROOT)/include) \
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-I $(call SYSPATH, $(PROJ_SRC_ROOT)/include) \
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-I $(call SYSPATH, $(PROJ_SRC_ROOT)/lib/Target)
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LLVMTableGen = $(LLVM_TBLGEN) $(TableGen.Flags)
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Archive = $(AR) $(AR.Flags)
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LArchive = $(LLVMToolDir)/llvm-ar rcsf
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@ -1700,87 +1701,87 @@ TDFiles := $(strip $(wildcard $(PROJ_SRC_DIR)/*.td) \
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$(LLVM_SRC_ROOT)/include/llvm/CodeGen/ValueTypes.td) \
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$(wildcard $(LLVM_SRC_ROOT)/include/llvm/Intrinsics*.td)
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# All of these files depend on tblgen and the .td files.
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$(INCTMPFiles) : $(TBLGEN) $(TDFiles)
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# All .inc.tmp files depend on the .td files.
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$(INCTMPFiles) : $(TDFiles)
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$(TARGET:%=$(ObjDir)/%GenRegisterInfo.inc.tmp): \
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$(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) register info implementation with tblgen"
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$(Verb) $(TableGen) -gen-register-info -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-register-info -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenInstrInfo.inc.tmp): \
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$(ObjDir)/%GenInstrInfo.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenInstrInfo.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) instruction information with tblgen"
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$(Verb) $(TableGen) -gen-instr-info -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-instr-info -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenAsmWriter.inc.tmp): \
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$(ObjDir)/%GenAsmWriter.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenAsmWriter.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) assembly writer with tblgen"
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$(Verb) $(TableGen) -gen-asm-writer -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-asm-writer -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenAsmWriter1.inc.tmp): \
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$(ObjDir)/%GenAsmWriter1.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenAsmWriter1.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) assembly writer #1 with tblgen"
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$(Verb) $(TableGen) -gen-asm-writer -asmwriternum=1 -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-asm-writer -asmwriternum=1 -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenAsmMatcher.inc.tmp): \
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$(ObjDir)/%GenAsmMatcher.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenAsmMatcher.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) assembly matcher with tblgen"
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$(Verb) $(TableGen) -gen-asm-matcher -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-asm-matcher -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenMCCodeEmitter.inc.tmp): \
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$(ObjDir)/%GenMCCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir
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$(ObjDir)/%GenMCCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) MC code emitter with tblgen"
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$(Verb) $(TableGen) -gen-emitter -mc-emitter -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-emitter -mc-emitter -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenMCPseudoLowering.inc.tmp): \
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$(ObjDir)/%GenMCPseudoLowering.inc.tmp: %.td $(ObjDir)/.dir
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$(ObjDir)/%GenMCPseudoLowering.inc.tmp: %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) MC Pseudo instruction expander with tblgen"
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$(Verb) $(TableGen) -gen-pseudo-lowering -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-pseudo-lowering -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenCodeEmitter.inc.tmp): \
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$(ObjDir)/%GenCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir
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$(ObjDir)/%GenCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) code emitter with tblgen"
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$(Verb) $(TableGen) -gen-emitter -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-emitter -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenDAGISel.inc.tmp): \
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$(ObjDir)/%GenDAGISel.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenDAGISel.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) DAG instruction selector implementation with tblgen"
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$(Verb) $(TableGen) -gen-dag-isel -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-dag-isel -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenDisassemblerTables.inc.tmp): \
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$(ObjDir)/%GenDisassemblerTables.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenDisassemblerTables.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) disassembly tables with tblgen"
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$(Verb) $(TableGen) -gen-disassembler -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-disassembler -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenEDInfo.inc.tmp): \
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$(ObjDir)/%GenEDInfo.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenEDInfo.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) enhanced disassembly information with tblgen"
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$(Verb) $(TableGen) -gen-enhanced-disassembly-info -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-enhanced-disassembly-info -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenFastISel.inc.tmp): \
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$(ObjDir)/%GenFastISel.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenFastISel.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) \"fast\" instruction selector implementation with tblgen"
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$(Verb) $(TableGen) -gen-fast-isel -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-fast-isel -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenSubtargetInfo.inc.tmp): \
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$(ObjDir)/%GenSubtargetInfo.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenSubtargetInfo.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) subtarget information with tblgen"
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$(Verb) $(TableGen) -gen-subtarget -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-subtarget -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenCallingConv.inc.tmp): \
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$(ObjDir)/%GenCallingConv.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenCallingConv.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) calling convention information with tblgen"
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$(Verb) $(TableGen) -gen-callingconv -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-callingconv -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenIntrinsics.inc.tmp): \
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$(ObjDir)/%GenIntrinsics.inc.tmp : %.td $(ObjDir)/.dir
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$(ObjDir)/%GenIntrinsics.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) intrinsics information with tblgen"
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$(Verb) $(TableGen) -gen-tgt-intrinsic -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-tgt-intrinsic -o $(call SYSPATH, $@) $<
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$(ObjDir)/ARMGenDecoderTables.inc.tmp : ARM.td $(ObjDir)/.dir
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$(ObjDir)/ARMGenDecoderTables.inc.tmp : ARM.td $(ObjDir)/.dir $(LLVM_TBLGEN)
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$(Echo) "Building $(<F) decoder tables with tblgen"
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$(Verb) $(TableGen) -gen-arm-decoder -o $(call SYSPATH, $@) $<
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$(Verb) $(LLVMTableGen) -gen-arm-decoder -o $(call SYSPATH, $@) $<
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clean-local::
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@ -1,26 +0,0 @@
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if( ${LLVM_TABLEGEN} STREQUAL "tblgen" )
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set(CX_NATIVE_TG_DIR "${CMAKE_BINARY_DIR}/native")
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set(LLVM_TABLEGEN_EXE "${CX_NATIVE_TG_DIR}/bin/tblgen")
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add_custom_command(OUTPUT ${CX_NATIVE_TG_DIR}
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COMMAND ${CMAKE_COMMAND} -E make_directory ${CX_NATIVE_TG_DIR}
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COMMENT "Creating ${CX_NATIVE_TG_DIR}...")
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add_custom_command(OUTPUT ${CX_NATIVE_TG_DIR}/CMakeCache.txt
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COMMAND ${CMAKE_COMMAND} -UMAKE_TOOLCHAIN_FILE -DCMAKE_BUILD_TYPE=Release ${CMAKE_SOURCE_DIR}
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WORKING_DIRECTORY ${CX_NATIVE_TG_DIR}
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DEPENDS ${CX_NATIVE_TG_DIR}
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COMMENT "Configuring native TableGen...")
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add_custom_command(OUTPUT ${LLVM_TABLEGEN_EXE}
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COMMAND ${CMAKE_BUILD_TOOL}
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DEPENDS ${CX_NATIVE_TG_DIR}/CMakeCache.txt
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WORKING_DIRECTORY ${CX_NATIVE_TG_DIR}/utils/TableGen
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COMMENT "Building native TableGen...")
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add_custom_target(NativeTableGen DEPENDS ${LLVM_TABLEGEN_EXE})
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add_dependencies(tblgen NativeTableGen)
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set_directory_properties(PROPERTIES ADDITIONAL_MAKE_CLEAN_FILES ${CX_NATIVE_TG_DIR})
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endif()
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@ -2,7 +2,7 @@
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# Extra parameters for `tblgen' may come after `ofn' parameter.
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# Adds the name of the generated file to TABLEGEN_OUTPUT.
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macro(tablegen ofn)
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macro(tablegen project ofn)
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file(GLOB local_tds "*.td")
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file(GLOB_RECURSE global_tds "${LLVM_MAIN_SRC_DIR}/include/llvm/*.td")
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@ -14,14 +14,14 @@ macro(tablegen ofn)
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endif()
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add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${ofn}.tmp
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# Generate tablegen output in a temporary file.
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COMMAND ${LLVM_TABLEGEN_EXE} ${ARGN} -I ${CMAKE_CURRENT_SOURCE_DIR}
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COMMAND ${${project}_TABLEGEN_EXE} ${ARGN} -I ${CMAKE_CURRENT_SOURCE_DIR}
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-I ${LLVM_MAIN_SRC_DIR}/lib/Target -I ${LLVM_MAIN_INCLUDE_DIR}
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${LLVM_TARGET_DEFINITIONS_ABSOLUTE}
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-o ${CMAKE_CURRENT_BINARY_DIR}/${ofn}.tmp
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# The file in LLVM_TARGET_DEFINITIONS may be not in the current
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# directory and local_tds may not contain it, so we must
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# explicitly list it here:
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DEPENDS ${LLVM_TABLEGEN_EXE} ${local_tds} ${global_tds}
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DEPENDS ${${project}_TABLEGEN_EXE} ${local_tds} ${global_tds}
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${LLVM_TARGET_DEFINITIONS_ABSOLUTE}
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COMMENT "Building ${ofn}..."
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)
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@ -53,3 +53,73 @@ function(add_public_tablegen_target target)
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add_dependencies(${target} ${LLVM_COMMON_DEPENDS})
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endif( TABLEGEN_OUTPUT )
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endfunction()
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if(CMAKE_CROSSCOMPILING)
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set(CX_NATIVE_TG_DIR "${CMAKE_BINARY_DIR}/native")
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add_custom_command(OUTPUT ${CX_NATIVE_TG_DIR}
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COMMAND ${CMAKE_COMMAND} -E make_directory ${CX_NATIVE_TG_DIR}
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COMMENT "Creating ${CX_NATIVE_TG_DIR}...")
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add_custom_command(OUTPUT ${CX_NATIVE_TG_DIR}/CMakeCache.txt
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COMMAND ${CMAKE_COMMAND} -UMAKE_TOOLCHAIN_FILE -DCMAKE_BUILD_TYPE=Release
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-DLLVM_BUILD_POLLY=OFF ${CMAKE_SOURCE_DIR}
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WORKING_DIRECTORY ${CX_NATIVE_TG_DIR}
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DEPENDS ${CX_NATIVE_TG_DIR}
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COMMENT "Configuring native TableGen...")
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add_custom_target(ConfigureNativeTableGen DEPENDS ${CX_NATIVE_TG_DIR}/CMakeCache.txt)
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set_directory_properties(PROPERTIES ADDITIONAL_MAKE_CLEAN_FILES ${CX_NATIVE_TG_DIR})
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endif()
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macro(add_tablegen target project)
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set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_TOOLS_BINARY_DIR})
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add_llvm_utility(${target} ${ARGN})
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set(${project}_TABLEGEN "${target}" CACHE
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STRING "Native TableGen executable. Saves building one when cross-compiling.")
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# Upgrade existing LLVM_TABLEGEN setting.
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if(${project} STREQUAL LLVM)
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if(${LLVM_TABLEGEN} STREQUAL tblgen)
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set(LLVM_TABLEGEN "${target}" CACHE
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STRING "Native TableGen executable. Saves building one when cross-compiling."
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FORCE)
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endif()
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endif()
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# Effective tblgen executable to be used:
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set(${project}_TABLEGEN_EXE ${${project}_TABLEGEN} PARENT_SCOPE)
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if(CMAKE_CROSSCOMPILING)
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if( ${${project}_TABLEGEN} STREQUAL "${target}" )
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set(${project}_TABLEGEN_EXE "${CX_NATIVE_TG_DIR}/bin/${target}")
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set(${project}_TABLEGEN_EXE ${${project}_TABLEGEN_EXE} PARENT_SCOPE)
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add_custom_command(OUTPUT ${${project}_TABLEGEN_EXE}
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COMMAND ${CMAKE_BUILD_TOOL} ${target}
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DEPENDS ${CX_NATIVE_TG_DIR}/CMakeCache.txt
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WORKING_DIRECTORY ${CX_NATIVE_TG_DIR}
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COMMENT "Building native TableGen...")
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add_custom_target(${project}NativeTableGen DEPENDS ${${project}_TABLEGEN_EXE})
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add_dependencies(${project}NativeTableGen ConfigureNativeTableGen)
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add_dependencies(${target} ${project}NativeTableGen)
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endif()
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endif()
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target_link_libraries(${target} LLVMSupport LLVMTableGen)
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if( MINGW )
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target_link_libraries(${target} imagehlp psapi)
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if(CMAKE_SIZEOF_VOID_P MATCHES "8")
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set_target_properties(${target} PROPERTIES LINK_FLAGS -Wl,--stack,16777216)
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endif(CMAKE_SIZEOF_VOID_P MATCHES "8")
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endif( MINGW )
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if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD AND NOT BEOS )
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target_link_libraries(${target} pthread)
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endif()
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install(TARGETS ${target} RUNTIME DESTINATION bin)
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endmacro()
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@ -1,6 +1,6 @@
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set(LLVM_TARGET_DEFINITIONS Intrinsics.td)
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tablegen(Intrinsics.gen -gen-intrinsic)
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llvm_tablegen(Intrinsics.gen -gen-intrinsic)
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add_custom_target(intrinsics_gen ALL
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DEPENDS ${llvm_builded_incs_dir}/Intrinsics.gen)
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@ -1,18 +1,18 @@
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set(LLVM_TARGET_DEFINITIONS ARM.td)
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tablegen(ARMGenRegisterInfo.inc -gen-register-info)
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tablegen(ARMGenInstrInfo.inc -gen-instr-info)
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tablegen(ARMGenCodeEmitter.inc -gen-emitter)
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tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
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tablegen(ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
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tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(ARMGenDAGISel.inc -gen-dag-isel)
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tablegen(ARMGenFastISel.inc -gen-fast-isel)
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tablegen(ARMGenCallingConv.inc -gen-callingconv)
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tablegen(ARMGenSubtargetInfo.inc -gen-subtarget)
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tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
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tablegen(ARMGenDisassemblerTables.inc -gen-disassembler)
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llvm_tablegen(ARMGenRegisterInfo.inc -gen-register-info)
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llvm_tablegen(ARMGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(ARMGenCodeEmitter.inc -gen-emitter)
|
||||
llvm_tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
|
||||
llvm_tablegen(ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
|
||||
llvm_tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher)
|
||||
llvm_tablegen(ARMGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(ARMGenFastISel.inc -gen-fast-isel)
|
||||
llvm_tablegen(ARMGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(ARMGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
llvm_tablegen(ARMGenDisassemblerTables.inc -gen-disassembler)
|
||||
add_public_tablegen_target(ARMCommonTableGen)
|
||||
|
||||
add_llvm_target(ARMCodeGen
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
set(LLVM_TARGET_DEFINITIONS Alpha.td)
|
||||
|
||||
tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(AlphaGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(AlphaGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(AlphaGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(AlphaGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(AlphaGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(AlphaGenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(AlphaCommonTableGen)
|
||||
|
||||
add_llvm_target(AlphaCodeGen
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
set(LLVM_TARGET_DEFINITIONS Blackfin.td)
|
||||
|
||||
tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(BlackfinGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(BlackfinGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(BlackfinGenIntrinsics.inc -gen-tgt-intrinsic)
|
||||
llvm_tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(BlackfinGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(BlackfinGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(BlackfinGenIntrinsics.inc -gen-tgt-intrinsic)
|
||||
add_public_tablegen_target(BlackfinCommonTableGen)
|
||||
|
||||
add_llvm_target(BlackfinCodeGen
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
set(LLVM_TARGET_DEFINITIONS SPU.td)
|
||||
|
||||
tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(SPUGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(SPUGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(SPUGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(SPUGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(SPUGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(SPUGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(SPUGenCodeEmitter.inc -gen-emitter)
|
||||
llvm_tablegen(SPUGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(SPUGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(SPUGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(SPUGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(SPUGenCallingConv.inc -gen-callingconv)
|
||||
add_public_tablegen_target(CellSPUCommonTableGen)
|
||||
|
||||
add_llvm_target(CellSPUCodeGen
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
set(LLVM_TARGET_DEFINITIONS MBlaze.td)
|
||||
|
||||
tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(MBlazeGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(MBlazeGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
|
||||
tablegen(MBlazeGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
|
||||
tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
llvm_tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(MBlazeGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
|
||||
llvm_tablegen(MBlazeGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
|
||||
llvm_tablegen(MBlazeGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
|
||||
llvm_tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
add_public_tablegen_target(MBlazeCommonTableGen)
|
||||
|
||||
add_llvm_target(MBlazeCodeGen
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
set(LLVM_TARGET_DEFINITIONS MSP430.td)
|
||||
|
||||
tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(MSP430GenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(MSP430GenCallingConv.inc -gen-callingconv)
|
||||
tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(MSP430GenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(MSP430GenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(MSP430CommonTableGen)
|
||||
|
||||
add_llvm_target(MSP430CodeGen
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
set(LLVM_TARGET_DEFINITIONS Mips.td)
|
||||
|
||||
tablegen(MipsGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(MipsGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(MipsGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(MipsGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(MipsGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(MipsGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(MipsGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(MipsGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(MipsGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(MipsGenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(MipsCommonTableGen)
|
||||
|
||||
add_llvm_target(MipsCodeGen
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
set(LLVM_TARGET_DEFINITIONS PTX.td)
|
||||
|
||||
tablegen(PTXGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(PTXGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(PTXGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(PTXGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(PTXGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(PTXGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(PTXGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(PTXGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(PTXGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(PTXGenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(PTXCommonTableGen)
|
||||
|
||||
add_llvm_target(PTXCodeGen
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
set(LLVM_TARGET_DEFINITIONS PPC.td)
|
||||
|
||||
tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(PPCGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
|
||||
tablegen(PPCGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(PPCGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(PPCGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(PPCGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(PPCGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(PPCGenCodeEmitter.inc -gen-emitter)
|
||||
llvm_tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
|
||||
llvm_tablegen(PPCGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(PPCGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(PPCGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(PPCGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(PPCGenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(PowerPCCommonTableGen)
|
||||
|
||||
add_llvm_target(PowerPCCodeGen
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
set(LLVM_TARGET_DEFINITIONS Sparc.td)
|
||||
|
||||
tablegen(SparcGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(SparcGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(SparcGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(SparcGenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(SparcGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(SparcGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(SparcGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(SparcGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(SparcGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(SparcGenCallingConv.inc -gen-callingconv)
|
||||
add_public_tablegen_target(SparcCommonTableGen)
|
||||
|
||||
add_llvm_target(SparcCodeGen
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
set(LLVM_TARGET_DEFINITIONS SystemZ.td)
|
||||
|
||||
tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(SystemZGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(SystemZGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(SystemZGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(SystemZGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(SystemZGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(SystemZGenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(SystemZCommonTableGen)
|
||||
|
||||
add_llvm_target(SystemZCodeGen
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
set(LLVM_TARGET_DEFINITIONS X86.td)
|
||||
|
||||
tablegen(X86GenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
|
||||
tablegen(X86GenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(X86GenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
|
||||
tablegen(X86GenAsmMatcher.inc -gen-asm-matcher)
|
||||
tablegen(X86GenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(X86GenFastISel.inc -gen-fast-isel)
|
||||
tablegen(X86GenCallingConv.inc -gen-callingconv)
|
||||
tablegen(X86GenSubtargetInfo.inc -gen-subtarget)
|
||||
tablegen(X86GenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
llvm_tablegen(X86GenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
|
||||
llvm_tablegen(X86GenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(X86GenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
|
||||
llvm_tablegen(X86GenAsmMatcher.inc -gen-asm-matcher)
|
||||
llvm_tablegen(X86GenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(X86GenFastISel.inc -gen-fast-isel)
|
||||
llvm_tablegen(X86GenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(X86GenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(X86GenEDInfo.inc -gen-enhanced-disassembly-info)
|
||||
add_public_tablegen_target(X86CommonTableGen)
|
||||
|
||||
set(sources
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
set(LLVM_TARGET_DEFINITIONS XCore.td)
|
||||
|
||||
tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(XCoreGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(XCoreGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget)
|
||||
llvm_tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
|
||||
llvm_tablegen(XCoreGenInstrInfo.inc -gen-instr-info)
|
||||
llvm_tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
|
||||
llvm_tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
|
||||
llvm_tablegen(XCoreGenCallingConv.inc -gen-callingconv)
|
||||
llvm_tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget)
|
||||
add_public_tablegen_target(XCoreCommonTableGen)
|
||||
|
||||
add_llvm_target(XCoreCodeGen
|
||||
|
|
|
|||
|
|
@ -20,9 +20,9 @@ GENFILE:=$(PROJ_OBJ_ROOT)/include/llvm/Intrinsics.gen
|
|||
INTRINSICTD := $(PROJ_SRC_ROOT)/include/llvm/Intrinsics.td
|
||||
INTRINSICTDS := $(wildcard $(PROJ_SRC_ROOT)/include/llvm/Intrinsics*.td)
|
||||
|
||||
$(ObjDir)/Intrinsics.gen.tmp: $(ObjDir)/.dir $(INTRINSICTDS) $(TBLGEN)
|
||||
$(ObjDir)/Intrinsics.gen.tmp: $(ObjDir)/.dir $(INTRINSICTDS) $(LLVM_TBLGEN)
|
||||
$(Echo) Building Intrinsics.gen.tmp from Intrinsics.td
|
||||
$(Verb) $(TableGen) $(call SYSPATH, $(INTRINSICTD)) -o $(call SYSPATH, $@) -gen-intrinsic
|
||||
$(Verb) $(LLVMTableGen) $(call SYSPATH, $(INTRINSICTD)) -o $(call SYSPATH, $@) -gen-intrinsic
|
||||
|
||||
$(GENFILE): $(ObjDir)/Intrinsics.gen.tmp
|
||||
$(Verb) $(CMP) -s $@ $< || ( $(CP) $< $@ && \
|
||||
|
|
|
|||
|
|
@ -1,9 +1,7 @@
|
|||
set(LLVM_REQUIRES_EH 1)
|
||||
set(LLVM_REQUIRES_RTTI 1)
|
||||
|
||||
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_TOOLS_BINARY_DIR})
|
||||
|
||||
add_llvm_utility(tblgen
|
||||
add_tablegen(llvm-tblgen LLVM
|
||||
ARMDecoderEmitter.cpp
|
||||
AsmMatcherEmitter.cpp
|
||||
AsmWriterEmitter.cpp
|
||||
|
|
@ -42,15 +40,3 @@ add_llvm_utility(tblgen
|
|||
X86DisassemblerTables.cpp
|
||||
X86RecognizableInstr.cpp
|
||||
)
|
||||
target_link_libraries(tblgen LLVMSupport LLVMTableGen)
|
||||
if( MINGW )
|
||||
target_link_libraries(tblgen imagehlp psapi)
|
||||
if(CMAKE_SIZEOF_VOID_P MATCHES "8")
|
||||
set_target_properties(tblgen PROPERTIES LINK_FLAGS -Wl,--stack,16777216)
|
||||
endif(CMAKE_SIZEOF_VOID_P MATCHES "8")
|
||||
endif( MINGW )
|
||||
if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD AND NOT BEOS )
|
||||
target_link_libraries(tblgen pthread)
|
||||
endif()
|
||||
|
||||
install(TARGETS tblgen RUNTIME DESTINATION bin)
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
##===----------------------------------------------------------------------===##
|
||||
|
||||
LEVEL = ../..
|
||||
TOOLNAME = tblgen
|
||||
TOOLNAME = llvm-tblgen
|
||||
USEDLIBS = LLVMTableGen.a LLVMSupport.a
|
||||
REQUIRES_EH := 1
|
||||
REQUIRES_RTTI := 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user