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Iterate deterministically over register classes

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Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164190 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Silva 2012-09-19 01:47:01 +00:00
parent 90fee07298
commit decfdf548b
1 changed files with 3 additions and 2 deletions
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5
utils/TableGen/AsmMatcherEmitter.cpp
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@ -599,7 +599,8 @@ public:
std::vector<OperandMatchEntry> OperandMatchInfo;
/// Map of Register records to their class information.
std::map<Record*, ClassInfo*> RegisterClasses;
typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
RegisterClassesTy RegisterClasses;
/// Map of Predicate records to their subtarget information.
std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
@ -2043,7 +2044,7 @@ static void emitValidateOperandClass(AsmMatcherInfo &Info,
OS << " MatchClassKind OpKind;\n";
OS << " switch (Operand.getReg()) {\n";
OS << " default: OpKind = InvalidMatchClass; break;\n";
for (std::map<Record*, ClassInfo*>::iterator
for (AsmMatcherInfo::RegisterClassesTy::iterator
it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
it != ie; ++it)
OS << " case " << Info.Target.getName() << "::"