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https://github.com/c64scene-ar/llvm-6502.git
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Move SSE2 logical operations PAND/POR/PXOR/PANDN above SSE1 logical operations ANDPS/ORPS/XORPS/ANDNPS. This fixes a pattern ordering issue that meant that the SSE2 instructions could never be directly selected since the SSE1 patterns would always match first. This is largely moot with the ExeDepsFix pass, but I'm trying to audit for all such ordering issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147765 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
6202e45d53
commit
dfa5f573e7
@ -2651,6 +2651,69 @@ let Predicates = [HasAVX] in {
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OpSize, VEX;
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}
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//===---------------------------------------------------------------------===//
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// SSE2 - Packed Integer Logical Instructions
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//===---------------------------------------------------------------------===//
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let ExeDomain = SSEPackedInt in { // SSE integer instructions
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/// PDI_binop_rm - Simple SSE2 binary operator.
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multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
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X86MemOperand x86memop, bit IsCommutable = 0,
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bit Is2Addr = 1> {
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let isCommutable = IsCommutable in
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def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
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def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (OpVT (OpNode RC:$src1,
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(bitconvert (memop_frag addr:$src2)))))]>;
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}
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} // ExeDomain = SSEPackedInt
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// These are ordered here for pattern ordering requirements with the fp versions
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let Predicates = [HasAVX] in {
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defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
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i128mem, 0, 0>, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
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i128mem, 1>;
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defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
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i128mem, 1>;
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defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
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i128mem, 1>;
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defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
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i128mem, 0>;
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} // Constraints = "$src1 = $dst"
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let Predicates = [HasAVX2] in {
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defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
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i256mem, 0, 0>, VEX_4V;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Logical Instructions
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//===----------------------------------------------------------------------===//
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@ -3463,26 +3526,6 @@ multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
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[(set RC:$dst, (IntId2 RC:$src1, (i32 imm:$src2)))]>;
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}
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/// PDI_binop_rm - Simple SSE2 binary operator.
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multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
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X86MemOperand x86memop, bit IsCommutable = 0,
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bit Is2Addr = 1> {
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let isCommutable = IsCommutable in
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def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
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def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (OpVT (OpNode RC:$src1,
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(bitconvert (memop_frag addr:$src2)))))]>;
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}
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} // ExeDomain = SSEPackedInt
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// 128-bit Integer Arithmetic
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@ -3703,15 +3746,6 @@ defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
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int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
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VR128, 0>, VEX_4V;
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defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
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i128mem, 1, 0>, VEX_4V;
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defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
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i128mem, 0, 0>, VEX_4V;
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let ExeDomain = SSEPackedInt in {
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let neverHasSideEffects = 1 in {
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// 128-bit logical shifts.
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@ -3756,15 +3790,6 @@ defm VPSRADY : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
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int_x86_avx2_psra_d, int_x86_avx2_psrai_d,
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VR256, 0>, VEX_4V;
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defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
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i256mem, 1, 0>, VEX_4V;
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defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
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i256mem, 0, 0>, VEX_4V;
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let ExeDomain = SSEPackedInt in {
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let neverHasSideEffects = 1 in {
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// 128-bit logical shifts.
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@ -3809,15 +3834,6 @@ defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
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int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
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VR128>;
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defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
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i128mem, 1>;
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defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
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i128mem, 1>;
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defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
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i128mem, 1>;
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defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
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i128mem, 0>;
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let ExeDomain = SSEPackedInt in {
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let neverHasSideEffects = 1 in {
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// 128-bit logical shifts.
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