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Add support for binary encoding of ARM 'adr' instructions referencing constant

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pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120635 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-12-02 00:28:45 +00:00
parent 317bafb82c
commit dff84b0325
7 changed files with 65 additions and 41 deletions
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5
lib/MC/ELFObjectWriter.cpp
View File

@ -408,7 +408,7 @@ namespace {
case FK_PCRel_1:
case FK_PCRel_2:
case FK_PCRel_4:
case ARM::fixup_arm_pcrel_12:
case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_branch:
return true;
@ -1456,8 +1456,9 @@ unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target,
} else {
switch ((unsigned)Fixup.getKind()) {
default: llvm_unreachable("invalid fixup kind!");
case ARM::fixup_arm_pcrel_12:
case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_adr_pcrel_12:
assert(0 && "Unimplemented"); break;
case ARM::fixup_arm_branch:
return ELF::R_ARM_CALL; break;

7
lib/MC/MachObjectWriter.cpp
View File

@ -31,7 +31,12 @@ using namespace llvm::object;
// FIXME: this has been copied from (or to) X86AsmBackend.cpp
static unsigned getFixupKindLog2Size(unsigned Kind) {
switch (Kind) {
default: llvm_unreachable("invalid fixup kind!");
// FIXME: Until ARM has it's own relocation stuff spun off, it comes
// through here and we don't want it to puke all over. Any reasonable
// values will only come when ARM relocation support gets added, at which
// point this will be X86 only again and the llvm_unreachable can be
// re-enabled.
default: return 0;// llvm_unreachable("invalid fixup kind!");
case FK_PCRel_1:
case FK_Data_1: return 0;
case FK_PCRel_2:

21
lib/Target/ARM/ARMAsmBackend.cpp
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@ -7,8 +7,8 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/Target/TargetAsmBackend.h"
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMFixupKinds.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAssembler.h"
@ -21,6 +21,7 @@
#include "llvm/Support/ELF.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetAsmBackend.h"
#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
@ -67,7 +68,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
case ARM::fixup_arm_movt_hi16:
case ARM::fixup_arm_movw_lo16:
return Value;
case ARM::fixup_arm_pcrel_12: {
case ARM::fixup_arm_ldst_pcrel_12: {
bool isAdd = true;
// ARM PC-relative values are offset by 8.
Value -= 8;
@ -79,6 +80,19 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
Value |= isAdd << 23;
return Value;
}
case ARM::fixup_arm_adr_pcrel_12: {
// ARM PC-relative values are offset by 8.
Value -= 8;
unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
if ((int64_t)Value < 0) {
Value = -Value;
opc = 2; // 0b0010
}
assert(ARM_AM::getSOImmVal(Value) != -1 &&
"Out of range pc-relative fixup value!");
// Encode the immediate and shift the opcode into place.
return ARM_AM::getSOImmVal(Value) | (opc << 21);
}
case ARM::fixup_arm_branch:
// These values don't encode the low two bits since they're always zero.
// Offset by 8 just as above.
@ -200,8 +214,9 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
switch (Kind) {
default: llvm_unreachable("Unknown fixup kind!");
case FK_Data_4: return 4;
case ARM::fixup_arm_pcrel_12: return 3;
case ARM::fixup_arm_ldst_pcrel_12: return 3;
case ARM::fixup_arm_pcrel_10: return 3;
case ARM::fixup_arm_adr_pcrel_12: return 3;
case ARM::fixup_arm_branch: return 3;
}
}

18
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -726,13 +726,29 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
}
return;
}
case ARM::LEApcrel: {
// FIXME: Need to also handle globals and externals
assert (MI->getOperand(1).isCPI());
unsigned LabelId = MI->getOperand(1).getIndex();
MCSymbol *Sym = GetCPISymbol(LabelId);
const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Sym, OutContext);
MCInst TmpInst;
TmpInst.setOpcode(ARM::ADR);
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
// Add predicate operands.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
TmpInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM::LEApcrelJT: {
unsigned JTI = MI->getOperand(1).getIndex();
unsigned Id = MI->getOperand(2).getImm();
MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, Id);
const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(JTISymbol, OutContext);
MCInst TmpInst;
TmpInst.setOpcode(ARM::ADRadd);
TmpInst.setOpcode(ARM::ADR);
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
// Add predicate operands.

8
lib/Target/ARM/ARMFixupKinds.h
View File

@ -15,12 +15,16 @@
namespace llvm {
namespace ARM {
enum Fixups {
// fixup_arm_pcrel_12 - 12-bit PC relative relocation for symbol addresses
fixup_arm_pcrel_12 = FirstTargetFixupKind,
// fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
// addresses
fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
// fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
// used in VFP and Thumb2 instructions where the lower 2 bits are not encoded
// (so it's encoded as an 8-bit immediate).
fixup_arm_pcrel_10,
// fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
// instruction.
fixup_arm_adr_pcrel_12,
// fixup_arm_brnach - 24-bit PC relative relocation for direct branch
// instructions.
fixup_arm_branch,

24
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1184,8 +1184,9 @@ def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
// assembler.
let neverHasSideEffects = 1, isReMaterializable = 1 in
// The 'adr' mnemonic encodes differently if the label is before or after
// the instruction.
def ADRadd : AI1<0b0100, (outs GPR:$Rd), (ins adrlabel:$label),
// the instruction. The {24-21} opcode bits are set by the fixup, as we don't
// know until then which form of the instruction will be used.
def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label),
MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
bits<4> Rd;
bits<12> label;
@ -1195,23 +1196,8 @@ def ADRadd : AI1<0b0100, (outs GPR:$Rd), (ins adrlabel:$label),
let Inst{15-12} = Rd;
let Inst{11-0} = label;
}
def ADRsub : AI1<0b0010, (outs GPR:$Rd), (ins adrlabel:$label),
MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
bits<4> Rd;
bits<12> label;
let Inst{27-25} = 0b001;
let Inst{20} = 0;
let Inst{19-16} = 0b1111;
let Inst{15-12} = Rd;
let Inst{11-0} = label;
}
// FIXME: This should be a pseudo lowered to one of the above at MC lowering
// time. It may be interesting determining which of the two. Perhaps a fixup
// will be needed to do so? That would be kinda fugly.
def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
MiscFrm, IIC_iALUi,
"adr${p}\t$Rd, #$label", []>;
def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
Size4Bytes, IIC_iALUi, []>;
def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
(ins i32imm:$label, nohash_imm:$id, pred:$p),

23
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -45,12 +45,13 @@ public:
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[] = {
// name offset bits flags
{ "fixup_arm_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_movt_hi16", 0, 16, 0 },
{ "fixup_arm_movw_lo16", 0, 16, 0 },
// name off bits flags
{ "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_movt_hi16", 0, 16, 0 },
{ "fixup_arm_movw_lo16", 0, 16, 0 },
};
if (Kind < FirstTargetFixupKind)
@ -418,14 +419,10 @@ uint32_t ARMMCCodeEmitter::
getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpIdx);
// If the destination is an immediate, we have nothing to do.
if (MO.isImm()) return MO.getImm();
assert (MO.isExpr() && "Unexpected branch target type!");
assert (MO.isExpr() && "Unexpected adr target type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_adr_pcrel_12);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
// All of the information is in the fixup.
return 0;
}
@ -448,7 +445,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
++MCNumCPRelocations;