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Add support for binary encoding of ARM 'adr' instructions referencing constant
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120635 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7,8 +7,8 @@
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetAsmBackend.h"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMFixupKinds.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAssembler.h"
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@ -21,6 +21,7 @@
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetAsmBackend.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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@ -67,7 +68,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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case ARM::fixup_arm_movt_hi16:
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case ARM::fixup_arm_movw_lo16:
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return Value;
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case ARM::fixup_arm_pcrel_12: {
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case ARM::fixup_arm_ldst_pcrel_12: {
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bool isAdd = true;
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// ARM PC-relative values are offset by 8.
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Value -= 8;
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@ -79,6 +80,19 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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Value |= isAdd << 23;
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return Value;
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}
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case ARM::fixup_arm_adr_pcrel_12: {
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// ARM PC-relative values are offset by 8.
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Value -= 8;
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unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
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if ((int64_t)Value < 0) {
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Value = -Value;
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opc = 2; // 0b0010
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}
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assert(ARM_AM::getSOImmVal(Value) != -1 &&
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"Out of range pc-relative fixup value!");
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// Encode the immediate and shift the opcode into place.
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return ARM_AM::getSOImmVal(Value) | (opc << 21);
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}
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case ARM::fixup_arm_branch:
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// These values don't encode the low two bits since they're always zero.
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// Offset by 8 just as above.
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@ -200,8 +214,9 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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default: llvm_unreachable("Unknown fixup kind!");
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case FK_Data_4: return 4;
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case ARM::fixup_arm_pcrel_12: return 3;
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case ARM::fixup_arm_ldst_pcrel_12: return 3;
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case ARM::fixup_arm_pcrel_10: return 3;
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case ARM::fixup_arm_adr_pcrel_12: return 3;
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case ARM::fixup_arm_branch: return 3;
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}
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}
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