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[SystemZ] Add a definition of the CLC instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188162 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
parent
f37c8feb46
commit
e03a56d62f
@ -1701,6 +1701,7 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
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OPCODE(UDIVREM32);
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OPCODE(UDIVREM64);
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OPCODE(MVC);
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OPCODE(CLC);
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OPCODE(ATOMIC_SWAPW);
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OPCODE(ATOMIC_LOADW_ADD);
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OPCODE(ATOMIC_LOADW_SUB);
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@ -80,6 +80,10 @@ namespace SystemZISD {
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// MachineMemOperands rather than one.
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MVC,
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// Use CLC to compare two blocks of memory, with the same comments
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// as for MVC.
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CLC,
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// Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
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// ATOMIC_LOAD_<op>.
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//
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@ -1386,3 +1386,22 @@ class AtomicLoadWBinaryReg<SDPatternOperator operator>
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: AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
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class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
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: AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
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// Define an instruction that operates on two fixed-length blocks of memory.
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// The real instruction uses a bdladdr12onlylen8 for the first operand and a
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// bdaddr12only for the second, with the length of the second operand being
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// implicitly the same as the first. This arrangement matches the underlying
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// assembly syntax. However, for instruction selection it's easier to have
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// two normal bdaddr12onlys and a separate length operand, so define a pseudo
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// instruction for that too.
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multiclass MemorySS<string mnemonic, bits<8> opcode,
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SDPatternOperator operator> {
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def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
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bdaddr12only:$BD2),
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mnemonic##"\t$BDL1, $BD2", []>;
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let usesCustomInserter = 1 in
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def Wrapper : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
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imm32len8:$length),
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[(operator bdaddr12only:$dest, bdaddr12only:$src,
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imm32len8:$length)]>;
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}
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@ -334,15 +334,7 @@ def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
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// Memory-to-memory moves.
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let mayLoad = 1, mayStore = 1 in
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def MVC : InstSS<0xD2, (outs), (ins bdladdr12onlylen8:$BDL1,
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bdaddr12only:$BD2),
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"mvc\t$BDL1, $BD2", []>;
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let mayLoad = 1, mayStore = 1, usesCustomInserter = 1 in
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def MVCWrapper : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
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imm32len8:$length),
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[(z_mvc bdaddr12only:$dest, bdaddr12only:$src,
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imm32len8:$length)]>;
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defm MVC : MemorySS<"mvc", 0xD2, z_mvc>;
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defm LoadStore8_32 : MVCLoadStore<anyextloadi8, truncstorei8, i32,
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MVCWrapper, 1>;
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@ -1000,6 +992,10 @@ let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
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}
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defm : ZXB<z_ucmp, GR64, CLGFR>;
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// Memory-to-memory comparison.
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let mayLoad = 1, Defs = [CC] in
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defm CLC : MemorySS<"clc", 0xD5, z_clc>;
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//===----------------------------------------------------------------------===//
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// Atomic operations
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//===----------------------------------------------------------------------===//
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@ -54,7 +54,7 @@ def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6,
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SDTCisVT<4, i32>,
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SDTCisVT<5, i32>,
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SDTCisVT<6, i32>]>;
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def SDT_ZCopy : SDTypeProfile<0, 3,
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def SDT_ZMemMemLength : SDTypeProfile<0, 3,
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[SDTCisPtrTy<0>,
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SDTCisPtrTy<1>,
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SDTCisVT<2, i32>]>;
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@ -109,8 +109,10 @@ def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">;
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def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">;
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def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>;
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def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZCopy,
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def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength,
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[SDNPHasChain, SDNPMayLoad]>;
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//===----------------------------------------------------------------------===//
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// Pattern fragments
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@ -1333,6 +1333,42 @@
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# CHECK: chy %r15, 0
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0xe3 0xf0 0x00 0x00 0x00 0x79
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# CHECK: clc 0(1), 0
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0xd5 0x00 0x00 0x00 0x00 0x00
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# CHECK: clc 0(1), 0(%r1)
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0xd5 0x00 0x00 0x00 0x10 0x00
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# CHECK: clc 0(1), 0(%r15)
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0xd5 0x00 0x00 0x00 0xf0 0x00
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# CHECK: clc 0(1), 4095
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0xd5 0x00 0x00 0x00 0x0f 0xff
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# CHECK: clc 0(1), 4095(%r1)
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0xd5 0x00 0x00 0x00 0x1f 0xff
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# CHECK: clc 0(1), 4095(%r15)
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0xd5 0x00 0x00 0x00 0xff 0xff
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# CHECK: clc 0(1,%r1), 0
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0xd5 0x00 0x10 0x00 0x00 0x00
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# CHECK: clc 0(1,%r15), 0
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0xd5 0x00 0xf0 0x00 0x00 0x00
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# CHECK: clc 4095(1,%r1), 0
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0xd5 0x00 0x1f 0xff 0x00 0x00
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# CHECK: clc 4095(1,%r15), 0
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0xd5 0x00 0xff 0xff 0x00 0x00
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# CHECK: clc 0(256,%r1), 0
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0xd5 0xff 0x10 0x00 0x00 0x00
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# CHECK: clc 0(256,%r15), 0
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0xd5 0xff 0xf0 0x00 0x00 0x00
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# CHECK: clfhsi 0, 0
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0xe5 0x5d 0x00 0x00 0x00 0x00
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@ -4444,6 +4480,42 @@
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# CHECK: msy %r15, 0
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0xe3 0xf0 0x00 0x00 0x00 0x51
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# CHECK: mvc 0(1), 0
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0xd2 0x00 0x00 0x00 0x00 0x00
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# CHECK: mvc 0(1), 0(%r1)
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0xd2 0x00 0x00 0x00 0x10 0x00
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# CHECK: mvc 0(1), 0(%r15)
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0xd2 0x00 0x00 0x00 0xf0 0x00
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# CHECK: mvc 0(1), 4095
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0xd2 0x00 0x00 0x00 0x0f 0xff
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# CHECK: mvc 0(1), 4095(%r1)
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0xd2 0x00 0x00 0x00 0x1f 0xff
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# CHECK: mvc 0(1), 4095(%r15)
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0xd2 0x00 0x00 0x00 0xff 0xff
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# CHECK: mvc 0(1,%r1), 0
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0xd2 0x00 0x10 0x00 0x00 0x00
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# CHECK: mvc 0(1,%r15), 0
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0xd2 0x00 0xf0 0x00 0x00 0x00
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# CHECK: mvc 4095(1,%r1), 0
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0xd2 0x00 0x1f 0xff 0x00 0x00
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# CHECK: mvc 4095(1,%r15), 0
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0xd2 0x00 0xff 0xff 0x00 0x00
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# CHECK: mvc 0(256,%r1), 0
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0xd2 0xff 0x10 0x00 0x00 0x00
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# CHECK: mvc 0(256,%r15), 0
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0xd2 0xff 0xf0 0x00 0x00 0x00
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# CHECK: mvghi 0, 0
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0xe5 0x48 0x00 0x00 0x00 0x00
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@ -712,6 +712,50 @@
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cl %r0, -1
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cl %r0, 4096
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#CHECK: error: missing length in address
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#CHECK: clc 0, 0
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#CHECK: error: missing length in address
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#CHECK: clc 0(%r1), 0(%r1)
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#CHECK: error: invalid use of length addressing
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#CHECK: clc 0(1,%r1), 0(2,%r1)
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#CHECK: error: invalid operand
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#CHECK: clc 0(0,%r1), 0(%r1)
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#CHECK: error: invalid operand
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#CHECK: clc 0(257,%r1), 0(%r1)
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#CHECK: error: invalid operand
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#CHECK: clc -1(1,%r1), 0(%r1)
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#CHECK: error: invalid operand
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#CHECK: clc 4096(1,%r1), 0(%r1)
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#CHECK: error: invalid operand
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#CHECK: clc 0(1,%r1), -1(%r1)
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#CHECK: error: invalid operand
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#CHECK: clc 0(1,%r1), 4096(%r1)
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#CHECK: error: %r0 used in an address
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#CHECK: clc 0(1,%r0), 0(%r1)
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#CHECK: error: %r0 used in an address
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#CHECK: clc 0(1,%r1), 0(%r0)
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#CHECK: error: invalid use of indexed addressing
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#CHECK: clc 0(%r1,%r2), 0(%r1)
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#CHECK: error: invalid use of indexed addressing
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#CHECK: clc 0(1,%r2), 0(%r1,%r2)
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#CHECK: error: unknown token in expression
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#CHECK: clc 0(-), 0
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clc 0, 0
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clc 0(%r1), 0(%r1)
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clc 0(1,%r1), 0(2,%r1)
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clc 0(0,%r1), 0(%r1)
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clc 0(257,%r1), 0(%r1)
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clc -1(1,%r1), 0(%r1)
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clc 4096(1,%r1), 0(%r1)
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clc 0(1,%r1), -1(%r1)
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clc 0(1,%r1), 4096(%r1)
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clc 0(1,%r0), 0(%r1)
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clc 0(1,%r1), 0(%r0)
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clc 0(%r1,%r2), 0(%r1)
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clc 0(1,%r2), 0(%r1,%r2)
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clc 0(-), 0
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#CHECK: error: invalid operand
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#CHECK: clfhsi -1, 0
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#CHECK: error: invalid operand
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@ -2454,6 +2454,32 @@
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cl %r0, 4095(%r15,%r1)
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cl %r15, 0
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#CHECK: clc 0(1), 0 # encoding: [0xd5,0x00,0x00,0x00,0x00,0x00]
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#CHECK: clc 0(1), 0(%r1) # encoding: [0xd5,0x00,0x00,0x00,0x10,0x00]
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#CHECK: clc 0(1), 0(%r15) # encoding: [0xd5,0x00,0x00,0x00,0xf0,0x00]
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#CHECK: clc 0(1), 4095 # encoding: [0xd5,0x00,0x00,0x00,0x0f,0xff]
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#CHECK: clc 0(1), 4095(%r1) # encoding: [0xd5,0x00,0x00,0x00,0x1f,0xff]
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#CHECK: clc 0(1), 4095(%r15) # encoding: [0xd5,0x00,0x00,0x00,0xff,0xff]
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#CHECK: clc 0(1,%r1), 0 # encoding: [0xd5,0x00,0x10,0x00,0x00,0x00]
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#CHECK: clc 0(1,%r15), 0 # encoding: [0xd5,0x00,0xf0,0x00,0x00,0x00]
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#CHECK: clc 4095(1,%r1), 0 # encoding: [0xd5,0x00,0x1f,0xff,0x00,0x00]
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#CHECK: clc 4095(1,%r15), 0 # encoding: [0xd5,0x00,0xff,0xff,0x00,0x00]
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#CHECK: clc 0(256,%r1), 0 # encoding: [0xd5,0xff,0x10,0x00,0x00,0x00]
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#CHECK: clc 0(256,%r15), 0 # encoding: [0xd5,0xff,0xf0,0x00,0x00,0x00]
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clc 0(1), 0
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clc 0(1), 0(%r1)
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clc 0(1), 0(%r15)
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clc 0(1), 4095
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clc 0(1), 4095(%r1)
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clc 0(1), 4095(%r15)
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clc 0(1,%r1), 0
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clc 0(1,%r15), 0
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clc 4095(1,%r1), 0
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clc 4095(1,%r15), 0
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clc 0(256,%r1), 0
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clc 0(256,%r15), 0
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#CHECK: clfhsi 0, 0 # encoding: [0xe5,0x5d,0x00,0x00,0x00,0x00]
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#CHECK: clfhsi 4095, 0 # encoding: [0xe5,0x5d,0x0f,0xff,0x00,0x00]
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#CHECK: clfhsi 0, 65535 # encoding: [0xe5,0x5d,0x00,0x00,0xff,0xff]
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