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.set pc relative displacement bug: label should be moved down one instruction

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to just before the add r1, pc:

Before:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

Now:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
        mov r1, #PCRELV0
LPCRELL0:
        add r1, pc


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33744 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-02-01 03:04:49 +00:00
parent 736cefff85
commit e0c2b6b9a8
1 changed files with 6 additions and 6 deletions
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12
lib/Target/ARM/ARMInstrThumb.td
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@ -480,17 +480,17 @@ let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
// assembler.
def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label),
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+4))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"mov $dst, #PCRELV${:uid}\n\tadd $dst, pc")),
"${:private}PCRELL${:uid}+6))\n"),
!strconcat("\tmov $dst, #PCRELV${:uid}\n",
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
[]>;
def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+4))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"mov $dst, #PCRELV${:uid}\n\tadd $dst, pc")),
[]>;
!strconcat("\tmov $dst, #PCRELV${:uid}\n",
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
[]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns