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More DCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77231 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -163,12 +163,8 @@ namespace ARMII {
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///
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enum Op {
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ADDri,
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ADDrs,
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ADDrr,
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MOVr,
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SUBri,
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SUBrs,
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SUBrr
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SUBri
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};
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}
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@ -66,12 +66,8 @@ unsigned ARMInstrInfo::
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getOpcode(ARMII::Op Op) const {
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switch (Op) {
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case ARMII::ADDri: return ARM::ADDri;
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case ARMII::ADDrs: return ARM::ADDrs;
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case ARMII::ADDrr: return ARM::ADDrr;
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case ARMII::MOVr: return ARM::MOVr;
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case ARMII::SUBri: return ARM::SUBri;
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case ARMII::SUBrs: return ARM::SUBrs;
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case ARMII::SUBrr: return ARM::SUBrr;
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default:
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break;
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}
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@ -33,12 +33,8 @@ unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
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switch (Op) {
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case ARMII::ADDri: return ARM::tADDi8;
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case ARMII::ADDrs: return 0;
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case ARMII::ADDrr: return ARM::tADDrr;
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case ARMII::MOVr: return ARM::tMOVr;
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case ARMII::SUBri: return ARM::tSUBi8;
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case ARMII::SUBrs: return 0;
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case ARMII::SUBrr: return ARM::tSUBrr;
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default:
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break;
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}
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@ -34,12 +34,8 @@ unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
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switch (Op) {
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case ARMII::ADDri: return ARM::t2ADDri;
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case ARMII::ADDrs: return ARM::t2ADDrs;
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case ARMII::ADDrr: return ARM::t2ADDrr;
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case ARMII::MOVr: return ARM::t2MOVr;
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case ARMII::SUBri: return ARM::t2SUBri;
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case ARMII::SUBrs: return ARM::t2SUBrs;
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case ARMII::SUBrr: return ARM::t2SUBrr;
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default:
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break;
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}
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