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This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Formatting fixes. Mostly long lines and blank spaces at end of lines. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172882 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1,4 +1,4 @@
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;===- ./lib/Target/Mips/Disassembler/LLVMBuild.txt --------------*- Conf -*--===;
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;===- ./lib/Target/Mips/Disassembler/LLVMBuild.txt -------------*- Conf -*--===;
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;
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; The LLVM Compiler Infrastructure
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;
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@ -1,4 +1,4 @@
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##===- lib/Target/Mips/Disassembler/Makefile ----------------*- Makefile -*-===##
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##===- lib/Target/Mips/Disassembler/Makefile ---------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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@ -28,7 +28,8 @@ using namespace llvm;
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static cl::opt<bool> NeverUseSaveRestore(
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"mips16-never-use-save-restore",
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cl::init(false),
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cl::desc("For testing ability to adjust stack pointer without save/restore instruction"),
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cl::desc("For testing ability to adjust stack pointer "
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"without save/restore instruction"),
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cl::Hidden);
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@ -169,15 +170,16 @@ unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
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}
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// Adjust SP by FrameSize bytes. Save RA, S0, S1
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void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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if (!NeverUseSaveRestore) {
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if (isUInt<11>(FrameSize))
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BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
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else {
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int Base = 2040; // should create template function like isUInt that returns largest
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// possible n bit unsigned integer
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int Base = 2040; // should create template function like isUInt that
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// returns largest possible n bit unsigned integer
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int64_t Remainder = FrameSize - Base;
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BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
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if (isInt<16>(-Remainder))
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@ -193,13 +195,16 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBloc
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// sw s1, -8[sp]
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// sw s0, -12[sp]
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MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), Mips::RA);
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MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
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Mips::RA);
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MIB1.addReg(Mips::SP);
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MIB1.addImm(-4);
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MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), Mips::S1);
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MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
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Mips::S1);
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MIB2.addReg(Mips::SP);
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MIB2.addImm(-8);
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MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), Mips::S0);
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MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
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Mips::S0);
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MIB3.addReg(Mips::SP);
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MIB3.addImm(-12);
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adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
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@ -207,15 +212,16 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBloc
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}
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// Adjust SP by FrameSize bytes. Restore RA, S0, S1
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void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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if (!NeverUseSaveRestore) {
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if (isUInt<11>(FrameSize))
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BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
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else {
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int Base = 2040; // should create template function like isUInt that returns largest
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// possible n bit unsigned integer
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int Base = 2040; // should create template function like isUInt that
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// returns largest possible n bit unsigned integer
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int64_t Remainder = FrameSize - Base;
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if (isInt<16>(Remainder))
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BuildMI(MBB, I, DL, get(Mips::AddiuSpImmX16)). addImm(Remainder);
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@ -229,15 +235,19 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicB
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// lw ra, -4[sp]
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// lw s1, -8[sp]
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// lw s0, -12[sp]
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MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), Mips::A0);
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MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
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Mips::A0);
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MIB1.addReg(Mips::SP);
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MIB1.addImm(-4);
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MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16), Mips::RA);
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MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
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Mips::RA);
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MIB0.addReg(Mips::A0);
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MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), Mips::S1);
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MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
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Mips::S1);
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MIB2.addReg(Mips::SP);
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MIB2.addImm(-8);
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MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), Mips::S0);
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MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
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Mips::S0);
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MIB3.addReg(Mips::SP);
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MIB3.addImm(-12);
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}
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@ -245,10 +255,12 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicB
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}
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// Adjust SP by Amount bytes where bytes can be up to 32bit number.
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// This can only be called at times that we know that there is at least one free register.
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// This can only be called at times that we know that there is at least one free
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// register.
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// This is clearly safe at prologue and epilogue.
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//
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void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Reg1, unsigned Reg2) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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@ -269,11 +281,13 @@ void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasi
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MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
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MIB3.addReg(Reg1);
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MIB3.addReg(Reg2, RegState::Kill);
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MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16), Mips::SP);
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MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
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Mips::SP);
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MIB4.addReg(Reg1, RegState::Kill);
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}
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void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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assert(false && "adjust stack pointer amount exceeded");
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}
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@ -257,7 +257,7 @@ class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
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class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
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string asmstr, InstrItinClass itin>:
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FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
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FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
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!strconcat(asmstr, "\t $rx"), [], itin> ;
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//
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@ -363,7 +363,7 @@ def imm32: Operand<i32>;
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def Constant32:
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MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
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def LwConstant32:
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MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm),
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"lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
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@ -430,7 +430,7 @@ def AddiuSpImmX16
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: FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
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let Defs = [SP];
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let Uses = [SP];
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}
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}
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//
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// Format: ADDU rz, rx, ry MIPS16e
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@ -1072,8 +1072,8 @@ class UncondBranch16_pat<SDNode OpNode, Instruction I>:
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// Indirect branch
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def: Mips16Pat<
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(brind CPU16Regs:$rs),
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(JrcRx16 CPU16Regs:$rs)>;
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(brind CPU16Regs:$rs),
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(JrcRx16 CPU16Regs:$rs)>;
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// Jump and Link (Call)
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@ -1562,7 +1562,7 @@ def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
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// hi/lo relocs
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def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
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def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
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(SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
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// wrapper_pic
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def : InstAlias<"xor $rs, $rt, $imm",
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(XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>,
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Requires<[NotMips64]>;
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def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0)>;
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def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt)>;
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def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0)>;
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def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt)>;
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def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegsOpnd:$rt,
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CPURegsOpnd:$rd, 0)>;
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def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegsOpnd:$rd, 0,
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CPURegsOpnd:$rt)>;
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def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegsOpnd:$rt,
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CPURegsOpnd:$rd, 0)>;
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def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegsOpnd:$rd, 0,
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CPURegsOpnd:$rt)>;
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions
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// This pass expands a branch or jump instruction into a long branch if its
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// offset is too large to fit into its immediate field.
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//
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// FIXME:
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// 1. Fix pc-region jump instructions which cross 256MB segment boundaries.
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// FIXME:
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// 1. Fix pc-region jump instructions which cross 256MB segment boundaries.
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// 2. If program has inline assembly statements whose size cannot be
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// determined accurately, load branch target addresses from the GOT.
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// determined accurately, load branch target addresses from the GOT.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-long-branch"
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