make machine operands fatter: give each one an up-pointer to the

machineinstr that owns it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45449 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-12-30 06:11:04 +00:00
parent 271000d545
commit e12d6abfdf
3 changed files with 21 additions and 6 deletions

View File

@ -166,11 +166,15 @@ public:
bool isImpReg = Op.isRegister() && Op.isImplicit();
assert((isImpReg || !OperandsComplete()) &&
"Trying to add an operand to a machine instr that is already done!");
if (isImpReg || NumImplicitOps == 0) // This is true most of the time.
if (isImpReg || NumImplicitOps == 0) {// This is true most of the time.
Operands.push_back(Op);
else
Operands.back().ParentMI = this;
} else {
// Insert a real operand before any implicit ones.
Operands.insert(Operands.begin()+Operands.size()-NumImplicitOps, Op);
unsigned OpNo = Operands.size()-NumImplicitOps;
Operands.insert(Operands.begin()+OpNo, Op);
Operands[OpNo].ParentMI = this;
}
}
//===--------------------------------------------------------------------===//

View File

@ -23,7 +23,8 @@ namespace llvm {
class MachineBasicBlock;
class GlobalValue;
class MachineInstr;
/// MachineOperand class - Representation of each machine instruction operand.
///
class MachineOperand {
@ -48,6 +49,9 @@ private:
int64_t immedVal; // For MO_Immediate and MO_*Index.
} contents;
/// ParentMI - This is the instruction that this operand is embedded into.
MachineInstr *ParentMI;
MachineOperandType opType:8; // Discriminate the union.
bool IsDef : 1; // True if this is a def, false if this is a use.
bool IsImp : 1; // True if this is an implicit def or use.
@ -69,7 +73,7 @@ private:
unsigned char subReg;
} auxInfo;
MachineOperand() {}
MachineOperand() : ParentMI(0) {}
void print(std::ostream &os) const;
void print(std::ostream *os) const { if (os) print(*os); }
@ -335,6 +339,7 @@ public:
IsDead = MO.IsDead;
opType = MO.opType;
auxInfo = MO.auxInfo;
ParentMI = MO.ParentMI;
return *this;
}

View File

@ -85,8 +85,10 @@ MachineInstr::MachineInstr(const MachineInstr &MI) {
Operands.reserve(MI.getNumOperands());
// Add operands
for (unsigned i = 0; i != MI.getNumOperands(); ++i)
for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
Operands.push_back(MI.getOperand(i));
Operands.back().ParentMI = this;
}
// Set parent, next, and prev to null
parent = 0;
@ -97,6 +99,10 @@ MachineInstr::MachineInstr(const MachineInstr &MI) {
MachineInstr::~MachineInstr() {
LeakDetector::removeGarbageObject(this);
#ifndef NDEBUG
for (unsigned i = 0, e = Operands.size(); i != e; ++i)
assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
#endif
}
/// getOpcode - Returns the opcode of this MachineInstr.