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Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,
allowing us to compile this: to this: %G1 = external global int %G2 = external global int void %test() { %X = load int* %G1 store int %X, int* %G2 ret void } test: save -96, %sp, %sp sethi %hi(G1), %l0 ld [%l0+%lo(G1)], %l0 sethi %hi(G2), %l1 st %l0, [%l1+%lo(G2)] restore %g0, %g0, %g0 retl nop instead of this: test: save -96, %sp, %sp sethi %hi(G1), %l0 or %g0, %lo(G1), %l1 ld [%l1+%l0], %l0 sethi %hi(G2), %l1 or %g0, %lo(G2), %l2 st %l0, [%l2+%l1] restore %g0, %g0, %g0 retl nop git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24812 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -186,7 +186,13 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
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void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
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printOperand(MI, opNum);
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O << "+";
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printOperand(MI, opNum+1);
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if (MI->getOperand(opNum+1).getType() == MachineOperand::MO_GlobalAddress) {
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O << "%lo(";
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printOperand(MI, opNum+1);
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O << ")";
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} else {
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printOperand(MI, opNum+1);
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}
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}
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@ -309,6 +309,9 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).Val))
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return false; // Let the reg+imm pattern catch this!
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if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
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Addr.getOperand(1).getOpcode() == V8ISD::Lo)
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return false; // Let the reg+imm pattern catch this!
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R1 = Select(Addr.getOperand(0));
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R2 = Select(Addr.getOperand(1));
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return true;
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@ -328,6 +331,16 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(1));
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(0));
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Select(Addr);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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@ -186,7 +186,13 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
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void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
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printOperand(MI, opNum);
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O << "+";
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printOperand(MI, opNum+1);
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if (MI->getOperand(opNum+1).getType() == MachineOperand::MO_GlobalAddress) {
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O << "%lo(";
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printOperand(MI, opNum+1);
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O << ")";
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} else {
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printOperand(MI, opNum+1);
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}
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}
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@ -309,6 +309,9 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).Val))
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return false; // Let the reg+imm pattern catch this!
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if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
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Addr.getOperand(1).getOpcode() == V8ISD::Lo)
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return false; // Let the reg+imm pattern catch this!
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R1 = Select(Addr.getOperand(0));
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R2 = Select(Addr.getOperand(1));
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return true;
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@ -328,6 +331,16 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(1));
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(0));
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Select(Addr);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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