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Add initial support for global variables, and fix a bug in addr mode selection

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where we didn't select the operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24811 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-18 02:10:39 +00:00
parent 04dd673aea
commit e357246c6b
4 changed files with 42 additions and 6 deletions
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18
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -34,6 +34,8 @@ namespace V8ISD {
CMPFCC, // Compare two FP operands, set fcc.
BRICC, // Branch to dest on icc condition
BRFCC, // Branch to dest on fcc condition
Hi, Lo, // Hi/Lo operations, typically on a global address.
};
}
@ -71,6 +73,9 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
// Custom legalize GlobalAddress nodes into LO/HI parts.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
// Sparc doesn't have sext_inreg, replace them with shl/sra
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
@ -239,6 +244,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
}
}
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
}
}
@ -297,8 +309,8 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).Val))
return false; // Let the reg+imm pattern catch this!
R1 = Addr.getOperand(0);
R2 = Addr.getOperand(1);
R1 = Select(Addr.getOperand(0));
R2 = Select(Addr.getOperand(1));
return true;
}
@ -312,7 +324,7 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
if (Predicate_simm13(CN)) {
Base = Addr.getOperand(0);
Base = Select(Addr.getOperand(0));
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
return true;
}

6
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -84,6 +84,8 @@ def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
//===----------------------------------------------------------------------===//
// Instructions
@ -657,3 +659,7 @@ def : Pat<(i32 simm13:$val),
// Arbitrary immediates.
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
// Global addresses
def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;

18
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@ -34,6 +34,8 @@ namespace V8ISD {
CMPFCC, // Compare two FP operands, set fcc.
BRICC, // Branch to dest on icc condition
BRFCC, // Branch to dest on fcc condition
Hi, Lo, // Hi/Lo operations, typically on a global address.
};
}
@ -71,6 +73,9 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
// Custom legalize GlobalAddress nodes into LO/HI parts.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
// Sparc doesn't have sext_inreg, replace them with shl/sra
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
@ -239,6 +244,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
}
}
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
}
}
@ -297,8 +309,8 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).Val))
return false; // Let the reg+imm pattern catch this!
R1 = Addr.getOperand(0);
R2 = Addr.getOperand(1);
R1 = Select(Addr.getOperand(0));
R2 = Select(Addr.getOperand(1));
return true;
}
@ -312,7 +324,7 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
if (Predicate_simm13(CN)) {
Base = Addr.getOperand(0);
Base = Select(Addr.getOperand(0));
Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
return true;
}

6
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -84,6 +84,8 @@ def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
//===----------------------------------------------------------------------===//
// Instructions
@ -657,3 +659,7 @@ def : Pat<(i32 simm13:$val),
// Arbitrary immediates.
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
// Global addresses
def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;