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Add initial support for global variables, and fix a bug in addr mode selection
where we didn't select the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24811 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -34,6 +34,8 @@ namespace V8ISD {
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CMPFCC, // Compare two FP operands, set fcc.
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BRICC, // Branch to dest on icc condition
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BRFCC, // Branch to dest on fcc condition
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Hi, Lo, // Hi/Lo operations, typically on a global address.
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};
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}
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@ -71,6 +73,9 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
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addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
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// Custom legalize GlobalAddress nodes into LO/HI parts.
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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// Sparc doesn't have sext_inreg, replace them with shl/sra
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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@ -239,6 +244,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
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}
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}
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
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SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
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SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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}
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}
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}
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@ -297,8 +309,8 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).Val))
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return false; // Let the reg+imm pattern catch this!
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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R1 = Select(Addr.getOperand(0));
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R2 = Select(Addr.getOperand(1));
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return true;
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}
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@ -312,7 +324,7 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if (Predicate_simm13(CN)) {
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Base = Addr.getOperand(0);
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Base = Select(Addr.getOperand(0));
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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@ -84,6 +84,8 @@ def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
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def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
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def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
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def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
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def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
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//===----------------------------------------------------------------------===//
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// Instructions
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@ -657,3 +659,7 @@ def : Pat<(i32 simm13:$val),
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// Arbitrary immediates.
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def : Pat<(i32 imm:$val),
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(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
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// Global addresses
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def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
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def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
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@ -34,6 +34,8 @@ namespace V8ISD {
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CMPFCC, // Compare two FP operands, set fcc.
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BRICC, // Branch to dest on icc condition
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BRFCC, // Branch to dest on fcc condition
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Hi, Lo, // Hi/Lo operations, typically on a global address.
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};
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}
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@ -71,6 +73,9 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
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addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
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// Custom legalize GlobalAddress nodes into LO/HI parts.
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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// Sparc doesn't have sext_inreg, replace them with shl/sra
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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@ -239,6 +244,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
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}
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}
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
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SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
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SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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}
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}
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}
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@ -297,8 +309,8 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).Val))
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return false; // Let the reg+imm pattern catch this!
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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R1 = Select(Addr.getOperand(0));
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R2 = Select(Addr.getOperand(1));
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return true;
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}
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@ -312,7 +324,7 @@ bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if (Predicate_simm13(CN)) {
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Base = Addr.getOperand(0);
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Base = Select(Addr.getOperand(0));
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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@ -84,6 +84,8 @@ def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
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def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
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def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
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def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
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def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
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//===----------------------------------------------------------------------===//
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// Instructions
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@ -657,3 +659,7 @@ def : Pat<(i32 simm13:$val),
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// Arbitrary immediates.
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def : Pat<(i32 imm:$val),
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(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
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// Global addresses
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def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
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def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
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