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Adds support for spilling previously allocated live intervals to
handle cases in which a register is unavailable for spill code. Adds LiveIntervalUnion::extract. While processing interferences on a live virtual register, reuses the same Query object for each physcial reg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118423 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -20,6 +20,44 @@
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#include <algorithm>
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using namespace llvm;
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// Find the first segment in the range [segBegin,segments_.end()) that
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// intersects with seg. If no intersection is found, return the first segI
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// such that segI.start >= seg.end
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//
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// This logic is tied to the underlying LiveSegments data structure. For now, we
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// use set::upper_bound to find the nearest starting position,
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// then reverse iterate to find the first overlap.
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//
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// Upon entry we have segBegin.start < seg.end
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// seg |--...
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// \ .
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// lvr ...-|
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//
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// After set::upper_bound, we have segI.start >= seg.start:
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// seg |--...
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// /
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// lvr |--...
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//
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// Assuming intervals are disjoint, if an intersection exists, it must be the
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// segment found or the one immediately preceeding it. We continue reverse
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// iterating to return the first overlapping segment.
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LiveIntervalUnion::SegmentIter
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LiveIntervalUnion::upperBound(SegmentIter segBegin,
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const LiveSegment &seg) {
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assert(seg.end > segBegin->start && "segment iterator precondition");
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// get the next LIU segment such that segI->start is not less than seg.start
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//
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// FIXME: Once we have a B+tree, we can make good use of segBegin as a hint to
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// upper_bound. For now, we're forced to search again from the root each time.
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SegmentIter segI = segments_.upper_bound(seg);
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while (segI != segBegin) {
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--segI;
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if (seg.start >= segI->end)
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return ++segI;
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}
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return segI;
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}
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// Merge a LiveInterval's segments. Guarantee no overlaps.
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//
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// Consider coalescing adjacent segments to save space, even though it makes
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@ -29,7 +67,7 @@ void LiveIntervalUnion::unify(LiveInterval &lvr) {
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SegmentIter segPos = segments_.begin();
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for (LiveInterval::iterator lvrI = lvr.begin(), lvrEnd = lvr.end();
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lvrI != lvrEnd; ++lvrI ) {
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LiveSegment segment(lvrI->start, lvrI->end, lvr);
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LiveSegment segment(lvrI->start, lvrI->end, &lvr);
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segPos = segments_.insert(segPos, segment);
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assert(*segPos == segment && "need equal val for equal key");
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#ifndef NDEBUG
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@ -47,40 +85,17 @@ void LiveIntervalUnion::unify(LiveInterval &lvr) {
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}
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}
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// Low-level helper to find the first segment in the range [segI,segEnd) that
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// intersects with a live virtual register segment, or segI.start >= lvr.end
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//
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// This logic is tied to the underlying LiveSegments data structure. For now, we
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// use a binary search within the vector to find the nearest starting position,
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// then reverse iterate to find the first overlap.
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//
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// Upon entry we have segI.start < lvrSeg.end
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// seg |--...
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// \ .
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// lvr ...-|
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//
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// After binary search, we have segI.start >= lvrSeg.start:
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// seg |--...
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// /
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// lvr |--...
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//
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// Assuming intervals are disjoint, if an intersection exists, it must be the
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// segment found or immediately behind it. We continue reverse iterating to
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// return the first overlap.
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typedef LiveIntervalUnion::SegmentIter SegmentIter;
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static SegmentIter upperBound(SegmentIter segBegin,
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SegmentIter segEnd,
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const LiveRange &lvrSeg) {
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assert(lvrSeg.end > segBegin->start && "segment iterator precondition");
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// get the next LIU segment such that setg.start is not less than
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// lvrSeg.start
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SegmentIter segI = std::upper_bound(segBegin, segEnd, lvrSeg.start);
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while (segI != segBegin) {
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--segI;
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if (lvrSeg.start >= segI->end)
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return ++segI;
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// Remove a live virtual register's segments from this union.
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void LiveIntervalUnion::extract(const LiveInterval &lvr) {
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// Remove each of the virtual register's live segments from the map.
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SegmentIter segPos = segments_.begin();
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for (LiveInterval::const_iterator lvrI = lvr.begin(), lvrEnd = lvr.end();
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lvrI != lvrEnd; ++lvrI) {
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LiveSegment seg(lvrI->start, lvrI->end, const_cast<LiveInterval*>(&lvr));
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segPos = upperBound(segPos, seg);
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assert(segPos != segments_.end() && "missing lvr segment");
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segments_.erase(segPos++);
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}
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return segI;
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}
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// Private interface accessed by Query.
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@ -102,8 +117,8 @@ static SegmentIter upperBound(SegmentIter segBegin,
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// Assumes that segments are sorted by start position in both
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// LiveInterval and LiveSegments.
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void LiveIntervalUnion::Query::findIntersection(InterferenceResult &ir) const {
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LiveInterval::iterator lvrEnd = lvr_.end();
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SegmentIter liuEnd = liu_.end();
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LiveInterval::iterator lvrEnd = lvr_->end();
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SegmentIter liuEnd = liu_->end();
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while (ir.liuSegI_ != liuEnd) {
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// Slowly advance the live virtual reg iterator until we surpass the next
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// segment in this union. If this is ever used for coalescing of fixed
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@ -115,7 +130,8 @@ void LiveIntervalUnion::Query::findIntersection(InterferenceResult &ir) const {
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break;
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// lvrSegI_ may have advanced far beyond liuSegI_,
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// do a fast intersection test to "catch up"
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ir.liuSegI_ = upperBound(ir.liuSegI_, liuEnd, *ir.lvrSegI_);
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LiveSegment seg(ir.lvrSegI_->start, ir.lvrSegI_->end, lvr_);
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ir.liuSegI_ = liu_->upperBound(ir.liuSegI_, seg);
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// Check if no liuSegI_ exists with lvrSegI_->start < liuSegI_.end
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if (ir.liuSegI_ == liuEnd)
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break;
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@ -135,7 +151,7 @@ LiveIntervalUnion::Query::firstInterference() {
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if (firstInterference_ != LiveIntervalUnion::InterferenceResult()) {
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return firstInterference_;
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}
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firstInterference_ = InterferenceResult(lvr_.begin(), liu_.begin());
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firstInterference_ = InterferenceResult(lvr_->begin(), liu_->begin());
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findIntersection(firstInterference_);
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return firstInterference_;
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}
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@ -147,12 +163,12 @@ bool LiveIntervalUnion::Query::nextInterference(InterferenceResult &ir) const {
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// Advance either the lvr or liu segment to ensure that we visit all unique
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// overlapping pairs.
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if (ir.lvrSegI_->end < ir.liuSegI_->end) {
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if (++ir.lvrSegI_ == lvr_.end())
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if (++ir.lvrSegI_ == lvr_->end())
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return false;
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}
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else {
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if (++ir.liuSegI_ == liu_.end()) {
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ir.lvrSegI_ = lvr_.end();
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if (++ir.liuSegI_ == liu_->end()) {
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ir.lvrSegI_ = lvr_->end();
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return false;
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}
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}
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@ -38,8 +38,8 @@ struct LiveSegment {
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SlotIndex end;
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LiveInterval *liveVirtReg;
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LiveSegment(SlotIndex s, SlotIndex e, LiveInterval &lvr)
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: start(s), end(e), liveVirtReg(&lvr) {}
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LiveSegment(SlotIndex s, SlotIndex e, LiveInterval *lvr)
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: start(s), end(e), liveVirtReg(lvr) {}
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bool operator==(const LiveSegment &ls) const {
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return start == ls.start && end == ls.end && liveVirtReg == ls.liveVirtReg;
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@ -111,12 +111,16 @@ public:
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SegmentIter begin() { return segments_.begin(); }
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SegmentIter end() { return segments_.end(); }
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// Return an iterator to the first segment after or including begin that
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// intersects with lvrSeg.
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SegmentIter upperBound(SegmentIter begin, const LiveSegment &seg);
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// Add a live virtual register to this union and merge its segments.
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// Holds a nonconst reference to the LVR for later maniplution.
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void unify(LiveInterval &lvr);
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// FIXME: needed by RegAllocGreedy
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//void extract(const LiveInterval &li);
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// Remove a live virtual register's segments from this union.
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void extract(const LiveInterval &lvr);
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/// Cache a single interference test result in the form of two intersecting
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/// segments. This allows efficiently iterating over the interferences. The
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@ -143,7 +147,7 @@ public:
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const LiveInterval::iterator &lvrSegPos() const { return lvrSegI_; }
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// Access the liu segment.
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const SegmentIter &liuSeg() const { return liuSegI_; }
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const SegmentIter &liuSegPos() const { return liuSegI_; }
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bool operator==(const InterferenceResult &ir) const {
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return lvrSegI_ == ir.lvrSegI_ && liuSegI_ == ir.liuSegI_;
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@ -156,18 +160,40 @@ public:
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/// Query interferences between a single live virtual register and a live
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/// interval union.
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class Query {
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LiveIntervalUnion &liu_;
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LiveInterval &lvr_;
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LiveIntervalUnion *liu_;
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LiveInterval *lvr_;
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InterferenceResult firstInterference_;
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// TBD: interfering vregs
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public:
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Query(LiveInterval &lvr, LiveIntervalUnion &liu): liu_(liu), lvr_(lvr) {}
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Query(): liu_(), lvr_() {}
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LiveInterval &lvr() const { return lvr_; }
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Query(LiveInterval *lvr, LiveIntervalUnion *liu): liu_(liu), lvr_(lvr) {}
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void clear() {
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liu_ = NULL;
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lvr_ = NULL;
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firstInterference_ = InterferenceResult();
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}
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void init(LiveInterval *lvr, LiveIntervalUnion *liu) {
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if (lvr_ == lvr) {
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// We currently allow query objects to be reused acrossed live virtual
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// registers, but always for the same live interval union.
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assert(liu_ == liu && "inconsistent initialization");
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// Retain cached results, e.g. firstInterference.
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return;
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}
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liu_ = liu;
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lvr_ = lvr;
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// Clear cached results.
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firstInterference_ = InterferenceResult();
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}
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LiveInterval &lvr() const { assert(lvr_ && "uninitialized"); return *lvr_; }
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bool isInterference(const InterferenceResult &ir) const {
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if (ir.lvrSegI_ != lvr_.end()) {
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if (ir.lvrSegI_ != lvr_->end()) {
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assert(overlap(*ir.lvrSegI_, *ir.liuSegI_) &&
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"invalid segment iterators");
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return true;
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@ -178,7 +204,8 @@ public:
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// Does this live virtual register interfere with the union.
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bool checkInterference() { return isInterference(firstInterference()); }
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// First pair of interfering segments, or a noninterfering result.
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// Get the first pair of interfering segments, or a noninterfering result.
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// This initializes the firstInterference_ cache.
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InterferenceResult firstInterference();
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// Treat the result as an iterator and advance to the next interfering pair
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@ -94,6 +94,10 @@ protected:
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LiveIntervals *lis_;
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LIUArray physReg2liu_;
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// Current queries, one per physreg. They must be reinitialized each time we
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// query on a new live virtual register.
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OwningArrayPtr<LiveIntervalUnion::Query> queries_;
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RegAllocBase(): tri_(0), vrm_(0), lis_(0) {}
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virtual ~RegAllocBase() {}
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@ -120,9 +124,15 @@ protected:
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virtual void releaseMemory();
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// Helper for checking interference between a live virtual register and a
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// physical register, including all its register aliases.
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bool checkPhysRegInterference(LiveIntervalUnion::Query &query, unsigned preg);
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// physical register, including all its register aliases. If an interference
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// exists, return the interfering register, which may be preg or an alias.
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unsigned checkPhysRegInterference(LiveInterval& lvr, unsigned preg);
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// Helper that spills all live virtual registers currently unified under preg
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// that interfere with the most recently queried lvr.
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void spillInterferences(unsigned preg,
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SmallVectorImpl<LiveInterval*> &splitLVRs);
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private:
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void seedLiveVirtRegs(LiveVirtRegQueue &lvrQ);
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};
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@ -17,10 +17,12 @@
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#include "RegAllocBase.h"
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#include "RenderMachineFunction.h"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "VirtRegRewriter.h"
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#include "llvm/Function.h"
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#include "llvm/PassAnalysisSupport.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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@ -31,13 +33,10 @@
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <vector>
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#include <queue>
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@ -84,6 +83,9 @@ public:
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virtual unsigned selectOrSplit(LiveInterval &lvr,
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SmallVectorImpl<LiveInterval*> &splitLVRs);
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void spillInterferences(unsigned preg,
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SmallVectorImpl<LiveInterval*> &splitLVRs);
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/// Perform register allocation.
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virtual bool runOnMachineFunction(MachineFunction &mf);
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@ -170,6 +172,8 @@ void RegAllocBase::init(const TargetRegisterInfo &tri, VirtRegMap &vrm,
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vrm_ = &vrm;
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lis_ = &lis;
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physReg2liu_.init(tri_->getNumRegs());
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// Cache an interferece query for each physical reg
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queries_.reset(new LiveIntervalUnion::Query[physReg2liu_.numRegs()]);
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}
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void RegAllocBase::LIUArray::clear() {
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@ -238,38 +242,61 @@ void RegAllocBase::allocatePhysRegs() {
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LVRVec splitLVRs;
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unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs);
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if (availablePhysReg) {
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assert(splitLVRs.empty() && "inconsistent splitting");
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DEBUG(dbgs() << "allocating: " << tri_->getName(availablePhysReg) <<
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" " << lvr << '\n');
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assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions");
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vrm_->assignVirt2Phys(lvr->reg, availablePhysReg);
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physReg2liu_[availablePhysReg].unify(*lvr);
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}
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else {
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for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end();
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lvrI != lvrEnd; ++lvrI) {
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assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) &&
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"expect split value in virtual register");
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lvrQ.push(*lvrI);
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}
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for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end();
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lvrI != lvrEnd; ++lvrI) {
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DEBUG(dbgs() << "queuing new interval: " << **lvrI << "\n");
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assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) &&
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"expect split value in virtual register");
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lvrQ.push(*lvrI);
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}
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}
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}
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// Check if this live virtual reg interferes with a physical register. If not,
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// then check for interference on each register that aliases with the physical
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// register.
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bool RegAllocBase::checkPhysRegInterference(LiveIntervalUnion::Query &query,
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unsigned preg) {
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if (query.checkInterference())
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return true;
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// register. Return the interfering register.
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unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &lvr,
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unsigned preg) {
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queries_[preg].init(&lvr, &physReg2liu_[preg]);
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if (queries_[preg].checkInterference())
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return preg;
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for (const unsigned *asI = tri_->getAliasSet(preg); *asI; ++asI) {
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// We assume it's very unlikely for a register in the alias set to also be
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// in the original register class. So we don't bother caching the
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// interference.
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LiveIntervalUnion::Query subQuery(query.lvr(), physReg2liu_[*asI] );
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if (subQuery.checkInterference())
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return true;
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queries_[*asI].init(&lvr, &physReg2liu_[*asI]);
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if (queries_[*asI].checkInterference())
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return *asI;
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}
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return false;
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return 0;
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}
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// Spill all live virtual registers currently unified under preg that interfere
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// with lvr.
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void RABasic::spillInterferences(unsigned preg,
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SmallVectorImpl<LiveInterval*> &splitLVRs) {
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SmallPtrSet<LiveInterval*, 8> spilledLVRs;
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LiveIntervalUnion::Query &query = queries_[preg];
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LiveIntervalUnion::InterferenceResult ir = query.firstInterference();
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assert(query.isInterference(ir) && "expect interference");
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do {
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LiveInterval *lvr = ir.liuSegPos()->liveVirtReg;
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if (!spilledLVRs.insert(lvr)) continue;
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// Spill the previously allocated lvr.
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SmallVector<LiveInterval*, 1> spillIs; // ignored
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spiller_->spill(lvr, splitLVRs, spillIs);
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} while (query.nextInterference(ir));
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for (SmallPtrSetIterator<LiveInterval*> lvrI = spilledLVRs.begin(),
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lvrEnd = spilledLVRs.end();
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lvrI != lvrEnd; ++lvrI ) {
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// Deallocate the interfering lvr by removing it from the preg union.
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physReg2liu_[preg].extract(**lvrI);
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}
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// After extracting segments, the query's results are invalid.
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query.clear();
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}
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//===----------------------------------------------------------------------===//
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@ -289,24 +316,59 @@ bool RegAllocBase::checkPhysRegInterference(LiveIntervalUnion::Query &query,
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// minimal, there is no value in caching them.
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unsigned RABasic::selectOrSplit(LiveInterval &lvr,
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SmallVectorImpl<LiveInterval*> &splitLVRs) {
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// Accumulate the min spill cost among the interferences, in case we spill.
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unsigned minSpillReg = 0;
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unsigned minSpillAlias = 0;
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float minSpillWeight = lvr.weight;
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||||
// Check for an available reg in this class.
|
||||
const TargetRegisterClass *trc = mri_->getRegClass(lvr.reg);
|
||||
for (TargetRegisterClass::iterator trcI = trc->allocation_order_begin(*mf_),
|
||||
trcEnd = trc->allocation_order_end(*mf_);
|
||||
trcI != trcEnd; ++trcI) {
|
||||
unsigned preg = *trcI;
|
||||
LiveIntervalUnion::Query query(lvr, physReg2liu_[preg]);
|
||||
if (!checkPhysRegInterference(query, preg)) {
|
||||
DEBUG(dbgs() << "\tallocating: " << tri_->getName(preg) << lvr << '\n');
|
||||
unsigned interfReg = checkPhysRegInterference(lvr, preg);
|
||||
if (interfReg == 0) {
|
||||
return preg;
|
||||
}
|
||||
LiveIntervalUnion::InterferenceResult interf =
|
||||
queries_[interfReg].firstInterference();
|
||||
float interfWeight = interf.liuSegPos()->liveVirtReg->weight;
|
||||
if (interfWeight < minSpillWeight ) {
|
||||
minSpillReg = interfReg;
|
||||
minSpillAlias = preg;
|
||||
minSpillWeight = interfWeight;
|
||||
}
|
||||
}
|
||||
DEBUG(dbgs() << "\tspilling: " << lvr << '\n');
|
||||
SmallVector<LiveInterval*, 1> spillIs; // ignored
|
||||
spiller_->spill(&lvr, splitLVRs, spillIs);
|
||||
if (minSpillReg == 0) {
|
||||
DEBUG(dbgs() << "spilling: " << lvr << '\n');
|
||||
SmallVector<LiveInterval*, 1> spillIs; // ignored
|
||||
spiller_->spill(&lvr, splitLVRs, spillIs);
|
||||
// The live virtual register requesting to be allocated was spilled. So tell
|
||||
// the caller not to allocate anything for this round.
|
||||
return 0;
|
||||
}
|
||||
// Free the cheapest physical register.
|
||||
spillInterferences(minSpillReg, splitLVRs);
|
||||
// Tell the caller to allocate to this newly freed physical register.
|
||||
assert(minSpillAlias != 0 && "need a free register after spilling");
|
||||
// We just spilled the first register that interferes with minSpillAlias. We
|
||||
// now assume minSpillAlias is free because only one register alias may
|
||||
// interfere at a time. e.g. we ignore predication.
|
||||
unsigned interfReg = checkPhysRegInterference(lvr, minSpillAlias);
|
||||
if (interfReg != 0) {
|
||||
dbgs() << "spilling cannot free " << tri_->getName(minSpillAlias) <<
|
||||
" for " << lvr.reg << " with interference " <<
|
||||
*queries_[interfReg].firstInterference().liuSegPos()->liveVirtReg << "\n";
|
||||
llvm_unreachable("Interference after spill.");
|
||||
}
|
||||
return minSpillAlias;
|
||||
}
|
||||
|
||||
// FIXME: update LiveStacks
|
||||
return 0;
|
||||
namespace llvm {
|
||||
Spiller *createInlineSpiller(MachineFunctionPass &pass,
|
||||
MachineFunction &mf,
|
||||
VirtRegMap &vrm);
|
||||
}
|
||||
|
||||
bool RABasic::runOnMachineFunction(MachineFunction &mf) {
|
||||
@ -323,6 +385,10 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
|
||||
RegAllocBase::init(*tm_->getRegisterInfo(), getAnalysis<VirtRegMap>(),
|
||||
getAnalysis<LiveIntervals>());
|
||||
|
||||
// We may want to force InlineSpiller for this register allocator. For
|
||||
// now we're also experimenting with the standard spiller.
|
||||
//
|
||||
//spiller_.reset(createInlineSpiller(*this, *mf_, *vrm_));
|
||||
spiller_.reset(createSpiller(*this, *mf_, *vrm_));
|
||||
|
||||
allocatePhysRegs();
|
||||
|
Loading…
Reference in New Issue
Block a user